Benjamin Kramer 6c59c7a6fd R600: Make helper functions static. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183744 91177308-0d34-0410-b5e6-96231b3b80d8		2013-06-11 13:32:25 +00:00
..
InstPrinter	Move passes from namespace llvm into anonymous namespaces. Sort includes while there.	2013-05-23 17:10:37 +00:00
MCTargetDesc	R600: Hide symbols of implementation details.	2013-05-23 15:43:05 +00:00
TargetInfo	R600: Remove unnecessary include	2013-06-07 20:28:43 +00:00
AMDGPU.h	R600: Rework subtarget info and remove AMDILDevice classes	2013-06-07 20:37:48 +00:00
AMDGPU.td	R600: Rework subtarget info and remove AMDILDevice classes	2013-06-07 20:37:48 +00:00
AMDGPUAsmPrinter.cpp	R600: Rework subtarget info and remove AMDILDevice classes	2013-06-07 20:37:48 +00:00
AMDGPUAsmPrinter.h	R600: Emit used GPRs count	2013-04-17 15:17:25 +00:00
AMDGPUCallingConv.td	R600: Rework subtarget info and remove AMDILDevice classes	2013-06-07 20:37:48 +00:00
AMDGPUConvertToISA.cpp
AMDGPUFrameLowering.cpp	R600: Fix calculation of stack offset in AMDGPUFrameLowering	2013-06-07 20:52:05 +00:00
AMDGPUFrameLowering.h
AMDGPUIndirectAddressing.cpp	Don't cache the instruction and register info from the TargetMachine, because	2013-06-07 20:28:55 +00:00
AMDGPUInstrInfo.cpp	R600: Rework subtarget info and remove AMDILDevice classes	2013-06-07 20:37:48 +00:00
AMDGPUInstrInfo.h
AMDGPUInstrInfo.td	Create an FPOW SDNode opcode def in the target independent .td file rather than in a specific backend.	2013-05-22 06:36:09 +00:00
AMDGPUInstructions.td	R600/SI: Add support for global loads	2013-06-03 17:39:43 +00:00
AMDGPUIntrinsics.td
AMDGPUISelLowering.cpp	R600/SI: Add a calling convention for compute shaders	2013-06-03 17:40:11 +00:00
AMDGPUISelLowering.h	R600/SI: Add support for work item and work group intrinsics	2013-06-03 17:40:18 +00:00
AMDGPUMachineFunction.cpp	R600: Initialize AMDGPUMachineFunction::ShaderType to ShaderType::COMPUTE	2013-04-26 18:32:24 +00:00
AMDGPUMachineFunction.h	R600/SI: Share code recording ShaderTypeAttribute between generations	2013-04-01 21:47:53 +00:00
AMDGPUMCInstLower.cpp
AMDGPUMCInstLower.h
AMDGPURegisterInfo.cpp	Don't cache the instruction and register info from the TargetMachine, because	2013-06-07 20:28:55 +00:00
AMDGPURegisterInfo.h	Don't cache the instruction and register info from the TargetMachine, because	2013-06-07 20:28:55 +00:00
AMDGPURegisterInfo.td	Make SubRegIndex size mandatory, following r183020.	2013-05-31 23:45:26 +00:00
AMDGPUStructurizeCFG.cpp	Silencing an MSVC warning about mixing bool and unsigned int.	2013-06-04 01:03:03 +00:00
AMDGPUSubtarget.cpp	R600: Rework subtarget info and remove AMDILDevice classes	2013-06-07 20:37:48 +00:00
AMDGPUSubtarget.h	R600: Rework subtarget info and remove AMDILDevice classes	2013-06-07 20:37:48 +00:00
AMDGPUTargetMachine.cpp	R600: Rework subtarget info and remove AMDILDevice classes	2013-06-07 20:37:48 +00:00
AMDGPUTargetMachine.h	Fix a leak on the r600 backend.	2013-05-23 03:31:47 +00:00
AMDILBase.td	R600: Move Subtarget feature definitions into AMDGPU.td	2013-06-07 20:28:49 +00:00
AMDILCFGStructurizer.cpp	R600: Rework subtarget info and remove AMDILDevice classes	2013-06-07 20:37:48 +00:00
AMDILInstrInfo.td	R600: Rework subtarget info and remove AMDILDevice classes	2013-06-07 20:37:48 +00:00
AMDILIntrinsicInfo.cpp	R600: Rework subtarget info and remove AMDILDevice classes	2013-06-07 20:37:48 +00:00
AMDILIntrinsicInfo.h
AMDILIntrinsics.td
AMDILISelDAGToDAG.cpp	R600: Rework subtarget info and remove AMDILDevice classes	2013-06-07 20:37:48 +00:00
AMDILISelLowering.cpp	R600: Rework subtarget info and remove AMDILDevice classes	2013-06-07 20:37:48 +00:00
AMDILRegisterInfo.td
CMakeLists.txt	R600: Rework subtarget info and remove AMDILDevice classes	2013-06-07 20:37:48 +00:00
LLVMBuild.txt
Makefile
Processors.td	R600: Rework subtarget info and remove AMDILDevice classes	2013-06-07 20:37:48 +00:00
R600ControlFlowFinalizer.cpp	R600: Anti dep better handled in tex clause	2013-06-07 23:30:26 +00:00
R600Defines.h	R600: Relax some vector constraints on Dot4.	2013-05-17 16:50:32 +00:00
R600EmitClauseMarkers.cpp	Don't cache the instruction and register info from the TargetMachine, because	2013-06-07 20:28:55 +00:00
R600ExpandSpecialInstrs.cpp	Don't cache the instruction and register info from the TargetMachine, because	2013-06-07 20:28:55 +00:00
R600InstrInfo.cpp	R600: Rework subtarget info and remove AMDILDevice classes	2013-06-07 20:37:48 +00:00
R600InstrInfo.h	R600: Rework subtarget info and remove AMDILDevice classes	2013-06-07 20:37:48 +00:00
R600Instructions.td	R600: Rework subtarget info and remove AMDILDevice classes	2013-06-07 20:37:48 +00:00
R600Intrinsics.td	R600: Improve texture handling	2013-05-17 16:50:20 +00:00
R600ISelLowering.cpp	R600: Make helper functions static.	2013-06-11 13:32:25 +00:00
R600ISelLowering.h	Don't cache the instruction and register info from the TargetMachine, because	2013-06-07 20:28:55 +00:00
R600MachineFunctionInfo.cpp	R600/SI: Share code recording ShaderTypeAttribute between generations	2013-04-01 21:47:53 +00:00
R600MachineFunctionInfo.h	Move passes from namespace llvm into anonymous namespaces. Sort includes while there.	2013-05-23 17:10:37 +00:00
R600MachineScheduler.cpp	R600: Use a refined heuristic to choose when switching clause	2013-06-07 23:30:34 +00:00
R600MachineScheduler.h	R600: Use a refined heuristic to choose when switching clause	2013-06-07 23:30:34 +00:00
R600OptimizeVectorRegisters.cpp	Don't cache the instruction and register info from the TargetMachine, because	2013-06-07 20:28:55 +00:00
R600Packetizer.cpp	R600: 3 op instructions have no write bit but the result are store in PV	2013-06-03 15:56:12 +00:00
R600RegisterInfo.cpp	Don't cache the instruction and register info from the TargetMachine, because	2013-06-07 20:28:55 +00:00
R600RegisterInfo.h	Don't cache the instruction and register info from the TargetMachine, because	2013-06-07 20:28:55 +00:00
R600RegisterInfo.td	R600: use capital letter for PV channel	2013-06-03 15:44:35 +00:00
R600Schedule.td	R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips	2013-04-30 00:14:17 +00:00
R600TextureIntrinsicsReplacer.cpp	Move passes from namespace llvm into anonymous namespaces. Sort includes while there.	2013-05-23 17:10:37 +00:00
SIAnnotateControlFlow.cpp	R600: Remove unnecessary include	2013-06-07 20:28:43 +00:00
SIDefines.h	R600/SI: Emit config values in register value pairs.	2013-04-15 17:51:35 +00:00
SIInsertWaits.cpp	Don't cache the instruction and register info from the TargetMachine, because	2013-06-07 20:28:55 +00:00
SIInstrFormats.td	R600/SI: Use the same names for VOP3 operands and encoding fields	2013-05-20 15:02:08 +00:00
SIInstrInfo.cpp	Don't cache the instruction and register info from the TargetMachine, because	2013-06-07 20:28:55 +00:00
SIInstrInfo.h	R600/SI: adjust writemask to only the used components	2013-04-10 08:39:08 +00:00
SIInstrInfo.td	Cast to the correct type. Pointer, not reference.	2013-06-06 05:39:29 +00:00
SIInstructions.td	R600: Rework subtarget info and remove AMDILDevice classes	2013-06-07 20:37:48 +00:00
SIIntrinsics.td	R600/SI: Add intrinsic for MIMG IMAGE_GET_RESINFO opcode	2013-05-06 23:02:19 +00:00
SIISelLowering.cpp	R600: Rework subtarget info and remove AMDILDevice classes	2013-06-07 20:37:48 +00:00
SIISelLowering.h	Don't cache the instruction and register info from the TargetMachine, because	2013-06-07 20:28:55 +00:00
SILowerControlFlow.cpp	Don't cache the instruction and register info from the TargetMachine, because	2013-06-07 20:28:55 +00:00
SIMachineFunctionInfo.cpp	R600/SI: Share code recording ShaderTypeAttribute between generations	2013-04-01 21:47:53 +00:00
SIMachineFunctionInfo.h	R600/SI: Share code recording ShaderTypeAttribute between generations	2013-04-01 21:47:53 +00:00
SIRegisterInfo.cpp	Don't cache the instruction and register info from the TargetMachine, because	2013-06-07 20:28:55 +00:00
SIRegisterInfo.h	Don't cache the instruction and register info from the TargetMachine, because	2013-06-07 20:28:55 +00:00
SIRegisterInfo.td	R600/SI: dynamical figure out the reg class of MIMG	2013-04-10 08:39:16 +00:00
SISchedule.td