Chandler Carruth 3eb4be0ace Revert r148686 (and r148694, a fix to it) due to a serious layering ... violation -- MC cannot depend on CodeGen. Specifically, the MCTargetDesc component of each target is actually a subcomponent of the MC library. As such, it cannot depend on the target-independent code generator, because MC itself cannot depend on the target-independent code generator. This change moved a flag from the ARM MCTargetDesc file ARMMCAsmInfo.cpp to the CodeGen layer in ARMException.cpp, leaving behind an 'extern' to refer back to it. That layering order isn't viable givin the constraints outlined above. Commandline flags are designed to be static specifically to avoid these types of bugs. Fixing this is likely going to require some non-trivial refactoring. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148759 91177308-0d34-0410-b5e6-96231b3b80d8		2012-01-24 00:30:17 +00:00
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ARM	Revert r148686 (and r148694, a fix to it) due to a serious layering	2012-01-24 00:30:17 +00:00
CBackend
CellSPU	Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.	2012-01-17 21:44:01 +00:00
CPP
Generic
Hexagon
MBlaze
Mips	Have getRegForInlineAsmConstraint return the correct register class when target	2012-01-04 02:45:01 +00:00
MSP430
PowerPC	AggressiveAntiDepBreaker needs to skip debug values because a debug value does not have a corresponding SUnit	2012-01-16 22:53:41 +00:00
PTX
SPARC
Thumb	Fix more places which should be checking for iOS, not darwin.	2012-01-04 01:55:04 +00:00
Thumb2	After r147827 and r147902, it's now possible for unallocatable registers to be	2012-01-14 01:53:46 +00:00
X86	Add support for selecting 256-bit PALIGNR.	2012-01-20 05:53:00 +00:00
XCore	FileCheck hygiene.	2012-01-05 00:43:34 +00:00