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InstPrinter
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MCTargetDesc
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R600: use native for alu
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2013-04-30 00:14:38 +00:00 |
TargetInfo
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AMDGPU.h
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R600: Packetize instructions
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2013-04-30 00:14:27 +00:00 |
AMDGPU.td
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AMDGPUAsmPrinter.cpp
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R600: config section now reports use of killgt
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2013-04-30 00:13:13 +00:00 |
AMDGPUAsmPrinter.h
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R600: Emit used GPRs count
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2013-04-17 15:17:25 +00:00 |
AMDGPUCallingConv.td
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R600/SI: Add support for buffer stores v2
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2013-04-05 23:31:51 +00:00 |
AMDGPUConvertToISA.cpp
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AMDGPUFrameLowering.cpp
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AMDGPUFrameLowering.h
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AMDGPUIndirectAddressing.cpp
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AMDGPUInstrInfo.cpp
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AMDGPUInstrInfo.h
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AMDGPUInstrInfo.td
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AMDGPUInstructions.td
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R600: Add pattern for the BFI_INT instruction
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2013-04-19 02:11:06 +00:00 |
AMDGPUIntrinsics.td
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AMDGPUISelLowering.cpp
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R600/SI: add mulhu/mulhs patterns
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2013-03-27 09:12:51 +00:00 |
AMDGPUISelLowering.h
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R600/SI: Add support for buffer stores v2
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2013-04-05 23:31:51 +00:00 |
AMDGPUMachineFunction.cpp
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R600: Initialize AMDGPUMachineFunction::ShaderType to ShaderType::COMPUTE
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2013-04-26 18:32:24 +00:00 |
AMDGPUMachineFunction.h
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R600/SI: Share code recording ShaderTypeAttribute between generations
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2013-04-01 21:47:53 +00:00 |
AMDGPUMCInstLower.cpp
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AMDGPUMCInstLower.h
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AMDGPURegisterInfo.cpp
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AMDGPURegisterInfo.h
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AMDGPURegisterInfo.td
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AMDGPUStructurizeCFG.cpp
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AMDGPUSubtarget.cpp
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R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions
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2013-04-30 00:13:39 +00:00 |
AMDGPUSubtarget.h
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R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions
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2013-04-30 00:13:39 +00:00 |
AMDGPUTargetMachine.cpp
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R600: Packetize instructions
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2013-04-30 00:14:27 +00:00 |
AMDGPUTargetMachine.h
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AMDIL7XXDevice.cpp
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AMDIL7XXDevice.h
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AMDIL.h
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AMDILBase.td
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R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions
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2013-04-30 00:13:39 +00:00 |
AMDILCFGStructurizer.cpp
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AMDILDevice.cpp
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AMDILDevice.h
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AMDILDeviceInfo.cpp
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R600: Add some new processor variants
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2013-04-30 00:13:27 +00:00 |
AMDILDeviceInfo.h
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AMDILDevices.h
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AMDILEvergreenDevice.cpp
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AMDILEvergreenDevice.h
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AMDILInstrInfo.td
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AMDILIntrinsicInfo.cpp
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AMDILIntrinsicInfo.h
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AMDILIntrinsics.td
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AMDILISelDAGToDAG.cpp
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ArrayRefize getMachineNode(). No functionality change.
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2013-04-19 22:22:57 +00:00 |
AMDILISelLowering.cpp
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AMDILNIDevice.cpp
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AMDILNIDevice.h
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AMDILPeepholeOptimizer.cpp
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AMDILRegisterInfo.td
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AMDILSIDevice.cpp
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AMDILSIDevice.h
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CMakeLists.txt
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R600: Packetize instructions
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2013-04-30 00:14:27 +00:00 |
LLVMBuild.txt
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Makefile
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Processors.td
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R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips
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2013-04-30 00:14:17 +00:00 |
R600ControlFlowFinalizer.cpp
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R600: use native for alu
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2013-04-30 00:14:38 +00:00 |
R600Defines.h
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R600: Add a Bank Swizzle operand
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2013-04-30 00:14:08 +00:00 |
R600EmitClauseMarkers.cpp
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R600: Fix last ALU of a clause being emitted in a separate clause
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2013-04-03 18:24:47 +00:00 |
R600ExpandSpecialInstrs.cpp
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R600InstrInfo.cpp
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R600: Always use texture cache for compute shaders
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2013-04-30 00:14:44 +00:00 |
R600InstrInfo.h
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R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips
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2013-04-30 00:14:17 +00:00 |
R600Instructions.td
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R600: use native for alu
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2013-04-30 00:14:38 +00:00 |
R600Intrinsics.td
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R600ISelLowering.cpp
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R600: Initialize BooleanVectorContents
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2013-04-24 23:56:18 +00:00 |
R600ISelLowering.h
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R600MachineFunctionInfo.cpp
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R600/SI: Share code recording ShaderTypeAttribute between generations
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2013-04-01 21:47:53 +00:00 |
R600MachineFunctionInfo.h
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R600: Use .AMDGPU.config section to emit stacksize
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2013-04-23 17:34:12 +00:00 |
R600MachineScheduler.cpp
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R600: Factorize maximum alu per clause in a single location
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2013-04-03 16:49:34 +00:00 |
R600MachineScheduler.h
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R600Packetizer.cpp
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R600: Packetize instructions
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2013-04-30 00:14:27 +00:00 |
R600RegisterInfo.cpp
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R600RegisterInfo.h
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R600RegisterInfo.td
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R600: use native for alu
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2013-04-30 00:14:38 +00:00 |
R600Schedule.td
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R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips
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2013-04-30 00:14:17 +00:00 |
SIAnnotateControlFlow.cpp
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SIDefines.h
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R600/SI: Emit config values in register value pairs.
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2013-04-15 17:51:35 +00:00 |
SIInsertWaits.cpp
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SIInstrFormats.td
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R600/SI: Use same names for corresponding MUBUF operands and encoding fields
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2013-04-05 23:31:44 +00:00 |
SIInstrInfo.cpp
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R600/SI: dynamical figure out the reg class of MIMG
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2013-04-10 08:39:16 +00:00 |
SIInstrInfo.h
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R600/SI: adjust writemask to only the used components
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2013-04-10 08:39:08 +00:00 |
SIInstrInfo.td
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R600/SI: Use InstFlag for VOP3 modifier operands
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2013-04-19 02:11:00 +00:00 |
SIInstructions.td
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R600: Add pattern for the BFI_INT instruction
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2013-04-19 02:11:06 +00:00 |
SIIntrinsics.td
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R600/SI: remove image sample writemask
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2013-04-10 08:39:01 +00:00 |
SIISelLowering.cpp
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ArrayRefize getMachineNode(). No functionality change.
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2013-04-19 22:22:57 +00:00 |
SIISelLowering.h
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R600/SI: dynamical figure out the reg class of MIMG
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2013-04-10 08:39:16 +00:00 |
SILowerControlFlow.cpp
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R600/SI: replace WQM intrinsic
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2013-03-26 14:03:50 +00:00 |
SIMachineFunctionInfo.cpp
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R600/SI: Share code recording ShaderTypeAttribute between generations
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2013-04-01 21:47:53 +00:00 |
SIMachineFunctionInfo.h
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R600/SI: Share code recording ShaderTypeAttribute between generations
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2013-04-01 21:47:53 +00:00 |
SIRegisterInfo.cpp
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R600/SI: switch back to RegPressure scheduling
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2013-03-26 14:04:02 +00:00 |
SIRegisterInfo.h
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R600/SI: switch back to RegPressure scheduling
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2013-03-26 14:04:02 +00:00 |
SIRegisterInfo.td
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R600/SI: dynamical figure out the reg class of MIMG
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2013-04-10 08:39:16 +00:00 |
SISchedule.td
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