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InstPrinter
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R600: Bank Swizzle now display SCL equivalent
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2013-06-29 19:32:29 +00:00 |
MCTargetDesc
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R600: Use correct encoding for Vertex Fetch instructions on Cayman
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2013-06-14 22:12:30 +00:00 |
TargetInfo
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R600: Remove unnecessary include
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2013-06-07 20:28:43 +00:00 |
AMDGPU.h
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R600: Rework subtarget info and remove AMDILDevice classes
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2013-06-07 20:37:48 +00:00 |
AMDGPU.td
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R600: Rework subtarget info and remove AMDILDevice classes
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2013-06-07 20:37:48 +00:00 |
AMDGPUAsmPrinter.cpp
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R600: Add local memory support via LDS
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2013-06-28 15:47:08 +00:00 |
AMDGPUAsmPrinter.h
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R600: Emit used GPRs count
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2013-04-17 15:17:25 +00:00 |
AMDGPUCallingConv.td
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R600/SI: Add support for v4i32 and v4f32 kernel args
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2013-06-25 02:39:25 +00:00 |
AMDGPUConvertToISA.cpp
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AMDGPUFrameLowering.cpp
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R600: Fix calculation of stack offset in AMDGPUFrameLowering
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2013-06-07 20:52:05 +00:00 |
AMDGPUFrameLowering.h
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R600: Support for indirect addressing v4
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2013-02-06 17:32:29 +00:00 |
AMDGPUIndirectAddressing.cpp
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Don't cache the instruction and register info from the TargetMachine, because
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2013-06-07 20:28:55 +00:00 |
AMDGPUInstrInfo.cpp
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R600: Use new getNamedOperandIdx function generated by TableGen
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2013-06-25 21:22:18 +00:00 |
AMDGPUInstrInfo.h
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R600: Use new getNamedOperandIdx function generated by TableGen
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2013-06-25 21:22:18 +00:00 |
AMDGPUInstrInfo.td
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Create an FPOW SDNode opcode def in the target independent .td file rather than in a specific backend.
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2013-05-22 06:36:09 +00:00 |
AMDGPUInstructions.td
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R600: Add local memory support via LDS
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2013-06-28 15:47:08 +00:00 |
AMDGPUIntrinsics.td
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R600: Add support for GROUP_BARRIER instruction
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2013-06-28 15:46:59 +00:00 |
AMDGPUISelLowering.cpp
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R600: Add local memory support via LDS
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2013-06-28 15:47:08 +00:00 |
AMDGPUISelLowering.h
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R600: Add local memory support via LDS
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2013-06-28 15:47:08 +00:00 |
AMDGPUMachineFunction.cpp
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R600: Add local memory support via LDS
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2013-06-28 15:47:08 +00:00 |
AMDGPUMachineFunction.h
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R600: Add local memory support via LDS
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2013-06-28 15:47:08 +00:00 |
AMDGPUMCInstLower.cpp
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Move all of the header files which are involved in modelling the LLVM IR
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2013-01-02 11:36:10 +00:00 |
AMDGPUMCInstLower.h
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R600: BB operand support for SI
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2012-12-17 15:14:54 +00:00 |
AMDGPURegisterInfo.cpp
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Don't cache the instruction and register info from the TargetMachine, because
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2013-06-07 20:28:55 +00:00 |
AMDGPURegisterInfo.h
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Don't cache the instruction and register info from the TargetMachine, because
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2013-06-07 20:28:55 +00:00 |
AMDGPURegisterInfo.td
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Make SubRegIndex size mandatory, following r183020.
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2013-05-31 23:45:26 +00:00 |
AMDGPUSubtarget.cpp
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R600: Rework subtarget info and remove AMDILDevice classes
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2013-06-07 20:37:48 +00:00 |
AMDGPUSubtarget.h
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R600: Rework subtarget info and remove AMDILDevice classes
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2013-06-07 20:37:48 +00:00 |
AMDGPUTargetMachine.cpp
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Move StructurizeCFG out of R600 to generic Transforms.
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2013-06-19 20:18:24 +00:00 |
AMDGPUTargetMachine.h
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Remove dead prototype.
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2013-06-18 06:24:14 +00:00 |
AMDILBase.td
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R600: Move Subtarget feature definitions into AMDGPU.td
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2013-06-07 20:28:49 +00:00 |
AMDILCFGStructurizer.cpp
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R600: Rework subtarget info and remove AMDILDevice classes
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2013-06-07 20:37:48 +00:00 |
AMDILInstrInfo.td
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R600: Rework subtarget info and remove AMDILDevice classes
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2013-06-07 20:37:48 +00:00 |
AMDILIntrinsicInfo.cpp
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R600: Rework subtarget info and remove AMDILDevice classes
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2013-06-07 20:37:48 +00:00 |
AMDILIntrinsicInfo.h
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Move all of the header files which are involved in modelling the LLVM IR
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2013-01-02 11:36:10 +00:00 |
AMDILIntrinsics.td
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R600/SI: Use MULADD_IEEE/V_MAD_F32 instruction for mad pattern
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2013-02-18 14:11:28 +00:00 |
AMDILISelDAGToDAG.cpp
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R600: Add local memory support via LDS
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2013-06-28 15:47:08 +00:00 |
AMDILISelLowering.cpp
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R600: Rework subtarget info and remove AMDILDevice classes
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2013-06-07 20:37:48 +00:00 |
AMDILRegisterInfo.td
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CMakeLists.txt
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Move StructurizeCFG out of R600 to generic Transforms.
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2013-06-19 20:18:24 +00:00 |
LLVMBuild.txt
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Makefile
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Processors.td
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R600/SI: Add processor types for each CIK variant
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2013-06-28 20:23:29 +00:00 |
R600ControlFlowFinalizer.cpp
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R600: Use EXPORT_RAT_INST_STORE_DWORD for stores on Cayman
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2013-06-14 22:12:24 +00:00 |
R600Defines.h
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R600: Add local memory support via LDS
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2013-06-28 15:47:08 +00:00 |
R600EmitClauseMarkers.cpp
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R600: Add support for GROUP_BARRIER instruction
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2013-06-28 15:46:59 +00:00 |
R600ExpandSpecialInstrs.cpp
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R600: Use new getNamedOperandIdx function generated by TableGen
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2013-06-25 21:22:18 +00:00 |
R600InstrFormats.td
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R600: Add local memory support via LDS
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2013-06-28 15:47:08 +00:00 |
R600InstrInfo.cpp
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R600: Fix an unitialized variable in R600InstrInfo.cpp
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2013-06-30 21:44:06 +00:00 |
R600InstrInfo.h
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R600: Support schedule and packetization of trans-only inst
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2013-06-29 19:32:43 +00:00 |
R600Instructions.td
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R600: Support schedule and packetization of trans-only inst
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2013-06-29 19:32:43 +00:00 |
R600Intrinsics.td
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R600: Improve texture handling
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2013-05-17 16:50:20 +00:00 |
R600ISelLowering.cpp
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R600: Add local memory support via LDS
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2013-06-28 15:47:08 +00:00 |
R600ISelLowering.h
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Don't cache the instruction and register info from the TargetMachine, because
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2013-06-07 20:28:55 +00:00 |
R600MachineFunctionInfo.cpp
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R600/SI: Share code recording ShaderTypeAttribute between generations
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2013-04-01 21:47:53 +00:00 |
R600MachineFunctionInfo.h
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Move passes from namespace llvm into anonymous namespaces. Sort includes while there.
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2013-05-23 17:10:37 +00:00 |
R600MachineScheduler.cpp
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R600: Support schedule and packetization of trans-only inst
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2013-06-29 19:32:43 +00:00 |
R600MachineScheduler.h
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R600: Support schedule and packetization of trans-only inst
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2013-06-29 19:32:43 +00:00 |
R600OptimizeVectorRegisters.cpp
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Don't cache the instruction and register info from the TargetMachine, because
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2013-06-07 20:28:55 +00:00 |
R600Packetizer.cpp
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R600: Support schedule and packetization of trans-only inst
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2013-06-29 19:32:43 +00:00 |
R600RegisterInfo.cpp
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Don't cache the instruction and register info from the TargetMachine, because
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2013-06-07 20:28:55 +00:00 |
R600RegisterInfo.h
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Don't cache the instruction and register info from the TargetMachine, because
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2013-06-07 20:28:55 +00:00 |
R600RegisterInfo.td
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R600: Support schedule and packetization of trans-only inst
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2013-06-29 19:32:43 +00:00 |
R600Schedule.td
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R600: Add local memory support via LDS
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2013-06-28 15:47:08 +00:00 |
R600TextureIntrinsicsReplacer.cpp
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Move passes from namespace llvm into anonymous namespaces. Sort includes while there.
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2013-05-23 17:10:37 +00:00 |
SIAnnotateControlFlow.cpp
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R600: Remove unnecessary include
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2013-06-07 20:28:43 +00:00 |
SIDefines.h
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R600/SI: Emit config values in register value pairs.
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2013-04-15 17:51:35 +00:00 |
SIInsertWaits.cpp
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Don't cache the instruction and register info from the TargetMachine, because
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2013-06-07 20:28:55 +00:00 |
SIInstrFormats.td
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R600/SI: Use the same names for VOP3 operands and encoding fields
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2013-05-20 15:02:08 +00:00 |
SIInstrInfo.cpp
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Don't cache the instruction and register info from the TargetMachine, because
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2013-06-07 20:28:55 +00:00 |
SIInstrInfo.h
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R600/SI: adjust writemask to only the used components
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2013-04-10 08:39:08 +00:00 |
SIInstrInfo.td
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Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change.
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2013-06-19 21:36:55 +00:00 |
SIInstructions.td
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R600: Add SI load support for v[24]i32 and store for v2i32
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2013-06-15 00:09:31 +00:00 |
SIIntrinsics.td
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R600/SI: Add intrinsic for MIMG IMAGE_GET_RESINFO opcode
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2013-05-06 23:02:19 +00:00 |
SIISelLowering.cpp
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R600: Consolidate expansion of v2i32/v4i32 ops for EG/SI
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2013-06-25 13:55:57 +00:00 |
SIISelLowering.h
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R600/SI: Report unaligned memory accesses as legal for > 32-bit types
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2013-06-25 02:39:35 +00:00 |
SILowerControlFlow.cpp
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Don't cache the instruction and register info from the TargetMachine, because
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2013-06-07 20:28:55 +00:00 |
SIMachineFunctionInfo.cpp
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R600/SI: Share code recording ShaderTypeAttribute between generations
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2013-04-01 21:47:53 +00:00 |
SIMachineFunctionInfo.h
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R600/SI: Share code recording ShaderTypeAttribute between generations
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2013-04-01 21:47:53 +00:00 |
SIRegisterInfo.cpp
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Don't cache the instruction and register info from the TargetMachine, because
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2013-06-07 20:28:55 +00:00 |
SIRegisterInfo.h
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Don't cache the instruction and register info from the TargetMachine, because
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2013-06-07 20:28:55 +00:00 |
SIRegisterInfo.td
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R600/SI: dynamical figure out the reg class of MIMG
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2013-04-10 08:39:16 +00:00 |
SISchedule.td
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