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llvm-6502/lib/Target/PowerPC
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Chris Lattner cafb67b250 fold and (shl X, C1), C2 -> rlwinm when possible. Many other cases are possible, 
include and (srl)    and the inverses (shl and) etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21820 91177308-0d34-0410-b5e6-96231b3b80d8
2005-05-09 17:39:48 +00:00
..
.cvsignore
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LICENSE.TXT
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Makefile
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PowerPC.td
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PowerPCInstrInfo.h
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PowerPCTargetMachine.h
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PPC32.td
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PPC32ISelSimple.cpp
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PPC32JITInfo.h
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PPC32RegisterInfo.td
Initial support for allocation condition registers
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PPC64.td
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PPC64CodeEmitter.cpp
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PPC64InstrInfo.cpp
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PPC64InstrInfo.h
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PPC64ISelPattern.cpp
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PPC64JITInfo.h
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PPC64RegisterInfo.cpp
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PPC64RegisterInfo.h
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PPC64RegisterInfo.td
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PPC64TargetMachine.h
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PPC.h
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PPCAsmPrinter.cpp
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PPCBranchSelector.cpp
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PPCCodeEmitter.cpp
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PPCFrameInfo.h
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PPCInstrBuilder.h
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PPCInstrFormats.td
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PPCInstrInfo.cpp
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PPCInstrInfo.h
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PPCInstrInfo.td
switch over the rest of the formats that use RC to use isDOT
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PPCISelPattern.cpp
fold and (shl X, C1), C2 -> rlwinm when possible. Many other cases are possible,
2005-05-09 17:39:48 +00:00
PPCJITInfo.cpp
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PPCJITInfo.h
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PPCRegisterInfo.cpp
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PPCRegisterInfo.h
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PPCRegisterInfo.td
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PPCRelocations.h
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PPCTargetMachine.cpp
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PPCTargetMachine.h
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README.txt
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README.txt 

TODO:
* condition register allocation
* gpr0 allocation
* implement do-loop -> bdnz transform
* implement powerpc-64 for darwin
* use stfiwx in float->int
* should hint to the branch select pass that it doesn't need to print the
  second unconditional branch, so we don't end up with things like:
	b .LBBl42__2E_expand_function_8_674	; loopentry.24
	b .LBBl42__2E_expand_function_8_42	; NewDefault
	b .LBBl42__2E_expand_function_8_42	; NewDefault

Currently failing tests that should pass:
* MultiSource
  |- Applications
  |  `- hbd: miscompilation