Tom Stellard 50c16fb65c R600/SI: Lower 64-bit immediates using REG_SEQUENCE ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205561 91177308-0d34-0410-b5e6-96231b3b80d8		2014-04-03 20:19:27 +00:00
..
AArch64	[AArch64] Lower SHL_PARTS, SRA_PARTS and SRL_PARTS	2014-03-27 16:28:09 +00:00
ARM	ARM: update even more tests	2014-04-03 17:35:22 +00:00
ARM64	ARM64: add regression test for r205519.	2014-04-03 09:36:05 +00:00
CPP
Generic
Hexagon
Inputs
Mips	[mips] Add more Octeon cnMips instructions	2014-04-02 18:40:43 +00:00
MSP430	Mark FPB as a reserved register when needed.	2014-04-02 13:13:56 +00:00
NVPTX	Fix for PR19099 - NVPTX produces invalid symbol names.	2014-03-31 15:56:26 +00:00
PowerPC	[PowerPC] Add some missing VSX bitcast patterns	2014-04-01 19:24:27 +00:00
R600	R600/SI: Lower 64-bit immediates using REG_SEQUENCE	2014-04-03 20:19:27 +00:00
SPARC
SystemZ
Thumb	ARM: cortex-m0 doesn't support unaligned memory access.	2014-04-02 19:28:13 +00:00
Thumb2	ARM: update even more tests	2014-04-03 17:35:22 +00:00
X86	llvm/test/CodeGen/X86/peephole-multiple-folds.ll: Relax expressions to satisfy win32.	2014-04-03 20:07:51 +00:00
XCore