Elena Demikhovsky 52981c4b60 I optimized the following patterns: ... sext <4 x i1> to <4 x i64> sext <4 x i8> to <4 x i64> sext <4 x i16> to <4 x i64> I'm running Combine on SIGN_EXTEND_IN_REG and revert SEXT patterns: (sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) -> (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT))) The sext_in_reg (v4i32 x) may be lowered to shl+sar operations. The "sar" does not exist on 64-bit operation, so lowering sext_in_reg (v4i64 x) has no vector solution. I also added a cost of this operations to the AVX costs table. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175619 91177308-0d34-0410-b5e6-96231b3b80d8		2013-02-20 12:42:54 +00:00
..
AArch64	AArch64: remove ConstantIsland pass & put literals in separate section.	2013-02-15 09:33:43 +00:00
ARM	ARM NEON: Merge a f32 bitcast of a v2i32 extractelt	2013-02-19 15:27:05 +00:00
CPP
Generic	For inline asm:	2013-01-11 18:12:39 +00:00
Hexagon	Hexagon: add support for predicate-GPR copies.	2013-02-13 22:56:34 +00:00
MBlaze
Mips	Expand pseudos/macros:	2013-02-20 05:45:15 +00:00
MSP430	Add support for varargs functions for msp430.	2012-11-21 17:28:27 +00:00
NVPTX	[NVPTX] Disable vector registers	2013-02-12 14:18:49 +00:00
PowerPC	DAGCombiner: Constant folding around pre-increment loads/stores	2013-02-08 21:35:47 +00:00
R600	R600/SI: Use MULADD_IEEE/V_MAD_F32 instruction for mad pattern	2013-02-18 14:11:28 +00:00
SI	Add R600 backend	2012-12-11 21:25:42 +00:00
SPARC	Use TargetTransformInfo to control switch-to-lookup table transformation	2012-10-30 11:23:25 +00:00
Thumb	Fix thumbv5e frame lowering assertion failure.	2013-02-20 12:21:33 +00:00
Thumb2	ARM: Allocation hints must make sure to be in the alloc order.	2013-02-19 18:55:36 +00:00
X86	I optimized the following patterns:	2013-02-20 12:42:54 +00:00
XCore	Fix handling of aliases to functions.	2012-11-16 21:12:38 +00:00