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InstPrinter
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MCTargetDesc
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TargetInfo
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AMDGPU.h
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SimplifyCFG: Use parallel-and and parallel-or mode to consolidate branch conditions
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2013-07-27 00:01:07 +00:00 |
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AMDGPU.td
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AMDGPUAsmPrinter.cpp
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AMDGPUAsmPrinter.h
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AMDGPUCallingConv.td
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R600: Use the same compute kernel calling convention for all GPUs
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2013-07-23 01:48:05 +00:00 |
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AMDGPUConvertToISA.cpp
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AMDGPUFrameLowering.cpp
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AMDGPUFrameLowering.h
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AMDGPUIndirectAddressing.cpp
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AMDGPUInstrInfo.cpp
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AMDGPUInstrInfo.h
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AMDGPUInstrInfo.td
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AMDGPUInstructions.td
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R600: Add support for 24-bit MUL instructions
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2013-07-23 01:48:42 +00:00 |
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AMDGPUIntrinsics.td
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AMDGPUISelDAGToDAG.cpp
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R600: Treat CONSTANT_ADDRESS loads like GLOBAL_ADDRESS loads when necessary
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2013-07-23 23:54:56 +00:00 |
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AMDGPUISelLowering.cpp
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R600/SI: Expand vector fp <-> int conversions
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2013-07-30 14:31:03 +00:00 |
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AMDGPUISelLowering.h
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DAGCombiner: Pass the correct type to TargetLowering::isF(Abs|Neg)Free
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2013-07-23 23:55:03 +00:00 |
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AMDGPUMachineFunction.cpp
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AMDGPUMachineFunction.h
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AMDGPUMCInstLower.cpp
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AMDGPUMCInstLower.h
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AMDGPURegisterInfo.cpp
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AMDGPURegisterInfo.h
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AMDGPURegisterInfo.td
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AMDGPUSubtarget.cpp
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AMDGPUSubtarget.h
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AMDGPUTargetMachine.cpp
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SimplifyCFG: Use parallel-and and parallel-or mode to consolidate branch conditions
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2013-07-27 00:01:07 +00:00 |
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AMDGPUTargetMachine.h
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SimplifyCFG: Use parallel-and and parallel-or mode to consolidate branch conditions
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2013-07-27 00:01:07 +00:00 |
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AMDGPUTargetTransformInfo.cpp
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SimplifyCFG: Use parallel-and and parallel-or mode to consolidate branch conditions
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2013-07-27 00:01:07 +00:00 |
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AMDILBase.td
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AMDILCFGStructurizer.cpp
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R600: Remove predicated_break inst
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2013-07-31 19:31:14 +00:00 |
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AMDILInstrInfo.td
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AMDILIntrinsicInfo.cpp
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AMDILIntrinsicInfo.h
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AMDILIntrinsics.td
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AMDILISelLowering.cpp
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AMDILRegisterInfo.td
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CMakeLists.txt
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SimplifyCFG: Use parallel-and and parallel-or mode to consolidate branch conditions
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2013-07-27 00:01:07 +00:00 |
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LLVMBuild.txt
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Makefile
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Processors.td
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R600ControlFlowFinalizer.cpp
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R600: Remove predicated_break inst
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2013-07-31 19:31:14 +00:00 |
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R600Defines.h
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R600EmitClauseMarkers.cpp
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R600ExpandSpecialInstrs.cpp
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R600: Remove predicated_break inst
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2013-07-31 19:31:14 +00:00 |
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R600InstrFormats.td
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Revert "R600: Use SchedModel enum for is{Trans,Vector}Only functions"
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2013-07-31 20:43:03 +00:00 |
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R600InstrInfo.cpp
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Revert "R600: Non vector only instruction can be scheduled on trans unit"
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2013-07-31 20:43:27 +00:00 |
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R600InstrInfo.h
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Revert "R600: Use SchedModel enum for is{Trans,Vector}Only functions"
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2013-07-31 20:43:03 +00:00 |
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R600Instructions.td
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Revert "R600: Use SchedModel enum for is{Trans,Vector}Only functions"
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2013-07-31 20:43:03 +00:00 |
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R600Intrinsics.td
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R600ISelLowering.cpp
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R600/SI: Expand vector fp <-> int conversions
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2013-07-30 14:31:03 +00:00 |
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R600ISelLowering.h
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R600MachineFunctionInfo.cpp
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R600MachineFunctionInfo.h
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R600MachineScheduler.cpp
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Revert "R600: Non vector only instruction can be scheduled on trans unit"
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2013-07-31 20:43:27 +00:00 |
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R600MachineScheduler.h
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Revert "R600: Non vector only instruction can be scheduled on trans unit"
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2013-07-31 20:43:27 +00:00 |
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R600OptimizeVectorRegisters.cpp
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R600: Do not mergevector after a vector reg is used
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2013-07-31 19:32:12 +00:00 |
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R600Packetizer.cpp
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Revert "R600: Non vector only instruction can be scheduled on trans unit"
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2013-07-31 20:43:27 +00:00 |
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R600RegisterInfo.cpp
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R600RegisterInfo.h
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R600RegisterInfo.td
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R600: Simplify assembly for KCache registers using the TableGen !add operator
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2013-07-23 01:48:08 +00:00 |
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R600Schedule.td
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R600TextureIntrinsicsReplacer.cpp
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SIAnnotateControlFlow.cpp
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SIDefines.h
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SIInsertWaits.cpp
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SIInstrFormats.td
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SIInstrInfo.cpp
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SIInstrInfo.h
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SIInstrInfo.td
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SIInstructions.td
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R600: Add support for 24-bit MAD instructions
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2013-07-23 01:48:49 +00:00 |
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SIIntrinsics.td
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SIISelLowering.cpp
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R600: Improve support for < 32-bit loads
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2013-07-23 01:48:35 +00:00 |
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SIISelLowering.h
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SILowerControlFlow.cpp
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SIMachineFunctionInfo.cpp
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SIMachineFunctionInfo.h
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SIRegisterInfo.cpp
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SIRegisterInfo.h
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SIRegisterInfo.td
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R600/SI: Add support for v2f32 loads
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2013-07-18 21:43:48 +00:00 |
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SISchedule.td
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