llvm-6502/test/CodeGen/R600
Tom Stellard d078070f6a R600: Fix R600ControlFlowFinalizer not considering VTX_READ 128 bit dst reg
Patch by: Vincent Lejeune

https://bugs.freedesktop.org/show_bug.cgi?id=64877

NOTE: This is a candidate for the 3.3 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182600 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-23 18:26:42 +00:00
..
128bit-kernel-args.ll
add.ll
alu-split.ll
and.ll
bfe_uint.ll
bfi_int.ll R600: Use depth first scheduling algorithm 2013-05-17 16:50:44 +00:00
call_fs.ll
cf_end.ll
dagcombiner-bug-illegal-vec4-int-to-fp.ll
disconnected-predset-break-bug.ll
elf.ll
elf.r600.ll
fabs.ll R600: Use bottom up scheduling algorithm 2013-05-17 16:50:56 +00:00
fadd.ll R600: Use bottom up scheduling algorithm 2013-05-17 16:50:56 +00:00
fcmp-cnd.ll
fcmp-cnde-int-args.ll
fcmp.ll
fdiv.ll R600: Use bottom up scheduling algorithm 2013-05-17 16:50:56 +00:00
floor.ll R600: Use bottom up scheduling algorithm 2013-05-17 16:50:56 +00:00
fmad.ll R600: Use bottom up scheduling algorithm 2013-05-17 16:50:56 +00:00
fmax.ll R600: Use bottom up scheduling algorithm 2013-05-17 16:50:56 +00:00
fmin.ll R600: Use bottom up scheduling algorithm 2013-05-17 16:50:56 +00:00
fmul.ll R600: Use bottom up scheduling algorithm 2013-05-17 16:50:56 +00:00
fmul.v4f32.ll
fp_to_sint.ll
fp_to_uint.ll
fsub.ll R600: Use bottom up scheduling algorithm 2013-05-17 16:50:56 +00:00
i8-to-double-to-float.ll
icmp-select-sete-reverse-args.ll
imm.ll
jump-address.ll
kcache-fold.ll
legalizedag-bug-expand-setcc.ll
lit.local.cfg
literals.ll
llvm.AMDGPU.imax.ll R600/SI: Add lit test coverage for the remaining patterns added recently 2013-05-14 09:53:30 +00:00
llvm.AMDGPU.imin.ll R600/SI: Add lit test coverage for the remaining patterns added recently 2013-05-14 09:53:30 +00:00
llvm.AMDGPU.mul.ll R600: Use bottom up scheduling algorithm 2013-05-17 16:50:56 +00:00
llvm.AMDGPU.tex.ll R600: Improve texture handling 2013-05-17 16:50:20 +00:00
llvm.AMDGPU.trunc.ll R600/SI: Add lit test coverage for the remaining patterns added recently 2013-05-14 09:53:30 +00:00
llvm.AMDGPU.umax.ll R600/SI: Add lit test coverage for the remaining patterns added recently 2013-05-14 09:53:30 +00:00
llvm.AMDGPU.umin.ll R600/SI: Add lit test coverage for the remaining patterns added recently 2013-05-14 09:53:30 +00:00
llvm.cos.ll
llvm.pow.ll R600: Use bottom up scheduling algorithm 2013-05-17 16:50:56 +00:00
llvm.SI.fs.interp.constant.ll
llvm.SI.imageload.ll
llvm.SI.resinfo.ll
llvm.SI.sample.ll
llvm.sin.ll
load-input-fold.ll R600: Lower int_load_input to copyFromReg instead of Register node 2013-05-17 16:51:06 +00:00
load.ll
loop-address.ll
lshl.ll
lshr.ll
mul.ll
mulhu.ll
or.ll
predicates.ll
pv.ll R600: Use bottom up scheduling algorithm 2013-05-17 16:50:56 +00:00
r600-encoding.ll R600: Use bottom up scheduling algorithm 2013-05-17 16:50:56 +00:00
README
reciprocal.ll
rotr.ll R600: Fix rotr.ll on non-asserts builds 2013-05-20 15:28:48 +00:00
schedule-fs-loop-nested-if.ll
schedule-fs-loop-nested.ll
schedule-fs-loop.ll
schedule-if-2.ll
schedule-if.ll
schedule-vs-if-nested-loop.ll
sdiv.ll
selectcc-cnd.ll
selectcc-cnde-int.ll
selectcc-icmp-select-float.ll
selectcc-opt.ll R600: Use bottom up scheduling algorithm 2013-05-17 16:50:56 +00:00
set-dx10.ll
setcc.ll
seto.ll
setuo.ll
shl.ll R600/SI: Add patterns for 64-bit shift operations 2013-05-20 15:02:12 +00:00
short-args.ll
sint_to_fp.ll
sra.ll
srl.ll
store.ll
store.r600.ll
sub.ll
udiv.ll
uint_to_fp.ll
uitofp.ll R600/SI: Add lit test coverage for the remaining patterns added recently 2013-05-14 09:53:30 +00:00
unsupported-cc.ll
urecip.ll
urem.ll
vselect.ll R600: Use bottom up scheduling algorithm 2013-05-17 16:50:56 +00:00
vtx-schedule.ll R600: Fix R600ControlFlowFinalizer not considering VTX_READ 128 bit dst reg 2013-05-23 18:26:42 +00:00
xor.ll

+==============================================================================+
| How to organize the lit tests                                                |
+==============================================================================+

- If you write a test for matching a single DAG opcode or intrinsic, it should
  go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)

- If you write a test that matches several DAG opcodes and checks for a single
  ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
  bfi_int.ll

- For all other tests, use your best judgement for organizing tests and naming
  the files.

+==============================================================================+
| Naming conventions                                                           |
+==============================================================================+

- Use dash '-' and not underscore '_' to separate words in file names, unless
  the file is named after a DAG opcode or ISA instruction that has an
  underscore '_' in its name.