llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-04 05:31:06 +00:00

History

Chris Lattner 6410552250 Fix a problem where lib/Target/TargetInstrInfo.h would include and use a header file from libcodegen. This violates a layering order: codegen depends on target, not the other way around. The fix to this is to split TII into two classes, TII and TargetInstrInfoImpl, which defines stuff that depends on libcodegen. It is defined in libcodegen, where the base is not. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45475 91177308-0d34-0410-b5e6-96231b3b80d8		2008-01-01 01:03:04 +00:00
..
Alpha.h
Alpha.td
AlphaAsmPrinter.cpp	Add new shorter predicates for testing machine operands for various types:	2007-12-30 23:10:15 +00:00
AlphaBranchSelector.cpp
AlphaCodeEmitter.cpp	Add new shorter predicates for testing machine operands for various types:	2007-12-30 23:10:15 +00:00
AlphaInstrFormats.td
AlphaInstrInfo.cpp	Fix a problem where lib/Target/TargetInstrInfo.h would include and use	2008-01-01 01:03:04 +00:00
AlphaInstrInfo.h	Fix a problem where lib/Target/TargetInstrInfo.h would include and use	2008-01-01 01:03:04 +00:00
AlphaInstrInfo.td
AlphaISelDAGToDAG.cpp	Rename SSARegMap -> MachineRegisterInfo in keeping with the idea	2007-12-31 04:13:23 +00:00
AlphaISelLowering.cpp	Rename SSARegMap -> MachineRegisterInfo in keeping with the idea	2007-12-31 04:13:23 +00:00
AlphaISelLowering.h
AlphaJITInfo.cpp
AlphaJITInfo.h
AlphaLLRP.cpp	Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm	2007-12-30 20:49:49 +00:00
AlphaRegisterInfo.cpp	Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the	2007-12-31 06:32:00 +00:00
AlphaRegisterInfo.h
AlphaRegisterInfo.td
AlphaRelocations.h
AlphaSchedule.td
AlphaSubtarget.cpp
AlphaSubtarget.h
AlphaTargetAsmInfo.cpp
AlphaTargetAsmInfo.h
AlphaTargetMachine.cpp
AlphaTargetMachine.h
Makefile
README.txt

README.txt

***

add gcc builtins for alpha instructions


***

custom expand byteswap into nifty 
extract/insert/mask byte/word/longword/quadword low/high
sequences

***

see if any of the extract/insert/mask operations can be added

***

match more interesting things for cmovlbc cmovlbs (move if low bit clear/set)

***

lower srem and urem

remq(i,j):  i - (j * divq(i,j)) if j != 0
remqu(i,j): i - (j * divqu(i,j)) if j != 0
reml(i,j):  i - (j * divl(i,j)) if j != 0
remlu(i,j): i - (j * divlu(i,j)) if j != 0

***

add crazy vector instructions (MVI):

(MIN|MAX)(U|S)(B8|W4) min and max, signed and unsigned, byte and word
PKWB, UNPKBW pack/unpack word to byte
PKLB UNPKBL pack/unpack long to byte
PERR pixel error (sum accross bytes of bytewise abs(i8v8 a - i8v8 b))

cmpbytes bytewise cmpeq of i8v8 a and i8v8 b (not part of MVI extentions)

this has some good examples for other operations that can be synthesised well 
from these rather meager vector ops (such as saturating add).
http://www.alphalinux.org/docs/MVI-full.html