Jim Grosbach b29b4dd988 Tweak ARM assembly parsing and printing of MSR instruction. ... The system register spec should be case insensitive. The preferred form for output with mask values of 4, 8, and 12 references APSR rather than CPSR. Update and tidy up tests accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135532 91177308-0d34-0410-b5e6-96231b3b80d8		2011-07-19 22:45:10 +00:00
..
arm-tests.txt	Tweak ARM assembly parsing and printing of MSR instruction.	2011-07-19 22:45:10 +00:00
dg.exp
invalid-Bcc-thumb.txt	A8.6.16 B	2011-04-12 00:14:49 +00:00
invalid-BFI-arm.txt
invalid-CPS2p-arm.txt
invalid-CPS3p-arm.txt
invalid-DMB-thumb.txt	Sanity check the option operand for DMB/DSB.	2011-04-08 19:18:07 +00:00
invalid-DSB-arm.txt	Sanity check the option operand for DMB/DSB.	2011-04-08 19:18:07 +00:00
invalid-LDC-form-arm.txt
invalid-LDR_POST-arm.txt	Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as	2011-04-11 18:34:12 +00:00
invalid-LDR_PRE-arm.txt	Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as	2011-04-11 18:34:12 +00:00
invalid-LDRB_POST-arm.txt	Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as	2011-04-11 18:34:12 +00:00
invalid-LDRD_PRE-thumb.txt	Add sanity check for Ld/St Dual forms of Thumb2 instructions.	2011-04-12 23:31:00 +00:00
invalid-LDRrs-arm.txt
invalid-LDRT-arm.txt
invalid-LSL-regform.txt
invalid-MCR-arm.txt
invalid-MOVr-arm.txt
invalid-MOVs-arm.txt
invalid-MOVs-LSL-arm.txt
invalid-MOVTi16-arm.txt
invalid-MSRi-arm.txt
invalid-RFEorLDMIA-arm.txt
invalid-RSC-arm.txt
invalid-SBFX-arm.txt
invalid-SMLAD-arm.txt
invalid-SRS-arm.txt
invalid-SSAT-arm.txt
invalid-STMIA_UPD-thumb.txt	Print out a debug message when the reglist fails the sanity check for Thumb Ld/St Multiple.	2011-04-12 17:09:04 +00:00
invalid-STRBrs-arm.txt	Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as	2011-04-11 18:34:12 +00:00
invalid-SXTB-arm.txt
invalid-t2Bcc-thumb.txt	Check for unallocated instruction encodings when disassembling Thumb Branch instructions (tBcc and t2Bcc).	2011-04-13 21:35:49 +00:00
invalid-t2LDRBT-thumb.txt	The LDR*T/STR*T (unpriviledged load/store) operations don't take SP or PC as Rt.	2011-04-13 21:04:32 +00:00
invalid-t2LDREXD-thumb.txt	Add sanity checkings for Thumb2 Load/Store Register Exclusive family of operations.	2011-04-14 19:13:28 +00:00
invalid-t2LDRSHi8-thumb.txt	Check the corner cases for t2LDRSHi12 correctly and mark invalid encodings as such.	2011-04-13 19:46:05 +00:00
invalid-t2LDRSHi12-thumb.txt	Check the corner cases for t2LDRSHi12 correctly and mark invalid encodings as such.	2011-04-13 19:46:05 +00:00
invalid-t2STR_POST-thumb.txt	Add bad register checks for Thumb2 Ld/St instructions.	2011-04-12 21:17:51 +00:00
invalid-t2STRD_PRE-thumb.txt	Add sanity check for Ld/St Dual forms of Thumb2 instructions.	2011-04-12 23:31:00 +00:00
invalid-t2STREXB-thumb.txt	Add sanity checkings for Thumb2 Load/Store Register Exclusive family of operations.	2011-04-14 19:13:28 +00:00
invalid-t2STREXD-thumb.txt	Add sanity checkings for Thumb2 Load/Store Register Exclusive family of operations.	2011-04-14 19:13:28 +00:00
invalid-UMAAL-arm.txt
invalid-UQADD8-arm.txt
invalid-VLD1DUPq8_UPD-arm.txt	The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions	2011-04-15 00:10:45 +00:00
invalid-VLD3DUPd32_UPD-thumb.txt	A8.6.315 VLD3 (single 3-element structure to all lanes)	2011-04-15 22:49:08 +00:00
invalid-VLDMSDB_UPD-arm.txt
invalid-VQADD-arm.txt
invalid-VST2b32_UPD-arm.txt
neon-tests.txt	Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues to simplify the path towards an auto-generated disassembler.	2011-07-15 18:46:47 +00:00
thumb-printf.txt	Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) should	2011-04-22 19:12:43 +00:00
thumb-tests.txt	Tweak ARM assembly parsing and printing of MSR instruction.	2011-07-19 22:45:10 +00:00