Ahmed Bougacha 6b96a388ed [AArch64] Don't force MVT::Untyped when selecting LD1LANEpost. ... The result is either an Untyped reg sequence, on ldN with N > 1, or just the type of the input vector, on ld1. Don't force Untyped. Instead, just use the type of the reg sequence. This mirrors the behavior of createTuple, which feeds the LD1*_POST. The narrow code path wasn't actually covered by tests, because V64 insert_vector_elt are widened to V128 before the LD1LANEpost combine has the chance to run, usually. The only case where it does run on V64 vectors is if the vector ops legalizer ran. So, tickle the code with a ctpop. Fixes PR23265. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235243 91177308-0d34-0410-b5e6-96231b3b80d8		2015-04-17 23:43:33 +00:00
..
AsmParser	[AArch64] Refactor AArch64NamedImmMapper to become dependent on subtarget features.	2015-04-16 12:15:27 +00:00
Disassembler	[AArch64] Add v8.1a "Limited Ordering Regions" extension	2015-04-16 15:30:43 +00:00
InstPrinter	[AArch64] Refactor AArch64NamedImmMapper to become dependent on subtarget features.	2015-04-16 12:15:27 +00:00
MCTargetDesc	[mc] Clean up emission of byte sequences	2015-04-17 11:12:43 +00:00
TargetInfo
Utils	[AArch64] Add v8.1a "Virtualization Host Extensions"	2015-04-16 15:38:58 +00:00
AArch64.h
AArch64.td	[AArch64] Rename v8.1a from "extension" to "architecture"	2015-04-01 14:49:29 +00:00
AArch64A53Fix835769.cpp
AArch64A57FPLoadBalancing.cpp
AArch64AddressTypePromotion.cpp
AArch64AdvSIMDScalarPass.cpp
AArch64AsmPrinter.cpp	DebugInfo: Gut DIVariable and DIGlobalVariable	2015-04-14 02:22:36 +00:00
AArch64BranchRelaxation.cpp
AArch64CallingConvention.h
AArch64CallingConvention.td
AArch64CleanupLocalDynamicTLSPass.cpp
AArch64CollectLOH.cpp	Change range-based for-loops to be -Wrange-loop-analysis clean.	2015-04-15 01:21:15 +00:00
AArch64ConditionalCompares.cpp
AArch64ConditionOptimizer.cpp
AArch64DeadRegisterDefinitionsPass.cpp
AArch64ExpandPseudoInsts.cpp	Transfer implicit operands when expanding the RET_ReallyLR pseudo instruction.	2015-03-30 22:45:56 +00:00
AArch64FastISel.cpp	Disable AArch64 fast-isel on big-endian call vector returns.	2015-04-16 21:19:36 +00:00
AArch64FrameLowering.cpp	[AArch64] Strengthen the code for the prologue insertion.	2015-04-10 23:14:34 +00:00
AArch64FrameLowering.h	[AArch64] Add support for dynamic stack alignment	2015-04-09 08:49:47 +00:00
AArch64InstrAtomics.td
AArch64InstrFormats.td	[AArch64] Add v8.1a "Limited Ordering Regions" extension	2015-04-16 15:30:43 +00:00
AArch64InstrInfo.cpp	[AArch64] Fix invalid use of references to BuildMI.	2015-04-16 11:37:40 +00:00
AArch64InstrInfo.h
AArch64InstrInfo.td	[AArch64] Add v8.1a "Limited Ordering Regions" extension	2015-04-16 15:30:43 +00:00
AArch64ISelDAGToDAG.cpp	[AArch64] Don't force MVT::Untyped when selecting LD1LANEpost.	2015-04-17 23:43:33 +00:00
AArch64ISelLowering.cpp	[AArch64] Avoid vector->load dependency cycles when creating LD1*post.	2015-04-17 21:02:30 +00:00
AArch64ISelLowering.h	AArch64: Don't lower ISD::SELECT to ISD::SELECT_CC	2015-04-07 17:33:05 +00:00
AArch64LoadStoreOptimizer.cpp
AArch64MachineCombinerPattern.h
AArch64MachineFunctionInfo.h
AArch64MCInstLower.cpp
AArch64MCInstLower.h
AArch64PBQPRegAlloc.cpp
AArch64PBQPRegAlloc.h
AArch64PerfectShuffle.h
AArch64PromoteConstant.cpp
AArch64RegisterInfo.cpp	[AArch64] Add support for dynamic stack alignment	2015-04-09 08:49:47 +00:00
AArch64RegisterInfo.h	[AArch64] Add support for dynamic stack alignment	2015-04-09 08:49:47 +00:00
AArch64RegisterInfo.td
AArch64SchedA53.td
AArch64SchedA57.td	[AArch64] Changes some SchedAlias to WriteRes for Cortex-A57.	2015-04-10 13:19:27 +00:00
AArch64SchedA57WriteRes.td
AArch64SchedCyclone.td
AArch64Schedule.td
AArch64SelectionDAGInfo.cpp
AArch64SelectionDAGInfo.h
AArch64StorePairSuppress.cpp
AArch64Subtarget.cpp	[AArch64] Rename v8.1a from "extension" to "architecture"	2015-04-01 14:49:29 +00:00
AArch64Subtarget.h	[AArch64] Rename v8.1a from "extension" to "architecture"	2015-04-01 14:49:29 +00:00
AArch64TargetMachine.cpp	[CodeGen] Split -enable-global-merge into ARM and AArch64 options.	2015-04-11 00:06:36 +00:00
AArch64TargetMachine.h
AArch64TargetObjectFile.cpp
AArch64TargetObjectFile.h
AArch64TargetTransformInfo.cpp
AArch64TargetTransformInfo.h
CMakeLists.txt
LLVMBuild.txt
Makefile