llvm-6502/lib/Target/ARM
Lauro Ramos Venancio 5293e7d5d6 Don't add or sub zero to sp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33142 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-12 20:52:27 +00:00
..
.cvsignore Ignore generated files 2006-05-27 01:23:30 +00:00
ARM.h move ARMCondCodeToString to ARMAsmPrinter.cpp 2006-11-02 15:00:02 +00:00
ARM.td getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd. 2006-05-18 00:12:58 +00:00
ARMAsmPrinter.cpp Fix for ARM weak symbols, patch by Lauro Ramos Venancio! 2006-12-21 22:59:58 +00:00
ARMCommon.cpp Build constants using instructions mov/orr or mvn/eor. 2007-01-12 20:35:49 +00:00
ARMCommon.h Build constants using instructions mov/orr or mvn/eor. 2007-01-12 20:35:49 +00:00
ARMFrameInfo.h use @ for comments 2006-08-25 17:55:16 +00:00
ARMInstrInfo.cpp Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead 2006-11-27 23:37:22 +00:00
ARMInstrInfo.h implement uncond branch insertion, mark branches with isBranch. 2006-10-24 16:47:57 +00:00
ARMInstrInfo.td implement missing compares 2006-12-31 18:52:39 +00:00
ARMISelDAGToDAG.cpp Build constants using instructions mov/orr or mvn/eor. 2007-01-12 20:35:49 +00:00
ARMMul.cpp Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead 2006-11-27 23:37:22 +00:00
ARMRegisterInfo.cpp Don't add or sub zero to sp. 2007-01-12 20:52:27 +00:00
ARMRegisterInfo.h Fix naming inconsistency. 2007-01-02 21:33:40 +00:00
ARMRegisterInfo.td initial support for frame pointers 2006-10-26 13:31:26 +00:00
ARMTargetAsmInfo.cpp Define StaticCtorsSection and StaticDtorsSection for ARM. 2006-12-28 13:13:00 +00:00
ARMTargetAsmInfo.h Break out target asm info into separate files. 2006-09-07 22:05:02 +00:00
ARMTargetMachine.cpp revert previous patch 2006-11-03 03:08:28 +00:00
ARMTargetMachine.h Implement a MachineFunctionPass to fix the mul instruction 2006-09-19 15:49:25 +00:00
Makefile added a skeleton of the ARM backend 2006-05-14 22:18:28 +00:00
README.txt add note 2006-12-11 23:56:10 +00:00

//===---------------------------------------------------------------------===//
// Random ideas for the ARM backend.
//===---------------------------------------------------------------------===//

Consider implementing a select with two conditional moves:

cmp x, y
moveq dst, a
movne dst, b

----------------------------------------------------------


%tmp1 = shl int %b, ubyte %c
%tmp4 = add int %a, %tmp1

compiles to

add r0, r0, r1, lsl r2

but

%tmp1 = shl int %b, ubyte %c
%tmp4 = add int %tmp1, %a

compiles to
mov r1, r1, lsl r2
add r0, r1, r0

---------------------------------------------------------
%tmp1 = shl int %b, ubyte 4
%tmp2 = add int %a, %tmp1

compiles to

mov r2, #4
add r0, r0, r1, lsl r2

should be

add r0, r0, r1, lsl #4

----------------------------------------------------------

add an offset to FLDS/FLDD/FSTD/FSTS addressing mode

----------------------------------------------------------

the function

void %f() {
entry:
	call void %g( int 1, int 2, int 3, int 4, int 5 )
	ret void
}

declare void %g(int, int, int, int, int)

Only needs 8 bytes of stack space. We currently allocate 16.

----------------------------------------------------------

32 x 32 -> 64 multiplications currently uses two instructions. We
should try to declare smull and umull as returning two values.

----------------------------------------------------------

Implement addressing modes 2 (ldrb) and 3 (ldrsb)

----------------------------------------------------------