Tim Northover 70b63374f2 ARM64: implement cunning optimisation from AArch64 ... A vector extract followed by a dup can become a single instruction even if the types don't match. AArch64 handled this in ISelLowering, but a few reasonably simple patterns can take care of it in TableGen, so that's where I've put it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206573 91177308-0d34-0410-b5e6-96231b3b80d8		2014-04-18 09:31:20 +00:00
..
AsmParser	ARM64AsmParser.cpp: Fix vg_leak in MC/ARM64/fp-encoding.s.	2014-04-15 13:22:11 +00:00
Disassembler	[MC] Require an MCContext when constructing an MCDisassembler.	2014-04-15 04:40:56 +00:00
InstPrinter	ARM64: [su]xtw use W regs as inputs, not X regs.	2014-04-17 20:47:31 +00:00
MCTargetDesc	AArch64/ARM64: produce correct relocation for conditional branches.	2014-04-16 15:27:52 +00:00
TargetInfo
Utils
ARM64.h
ARM64.td	[ARM64] Port over missing subtarget features, and CPU definitions from AArch64.	2014-04-14 17:38:00 +00:00
ARM64AddressTypePromotion.cpp
ARM64AdvSIMDScalarPass.cpp
ARM64AsmPrinter.cpp	AArch64/ARM64: port across stub handling for ELF C++ exceptions.	2014-04-16 11:52:55 +00:00
ARM64BranchRelaxation.cpp	[ARM64,C++11] Tidy up branch relaxation a bit w/ c++11.	2014-04-16 00:42:46 +00:00
ARM64CallingConv.h
ARM64CallingConvention.td	AArch64/ARM64: copy byval implementation from AArch64.	2014-04-18 09:30:52 +00:00
ARM64CleanupLocalDynamicTLSPass.cpp
ARM64CollectLOH.cpp	Fixing a compile error in debug versions of MSVC. It seems that the range-based for loop is confused by the DEBUG macro expansion unless a compound statement is used.	2014-04-16 11:15:57 +00:00
ARM64ConditionalCompares.cpp
ARM64DeadRegisterDefinitionsPass.cpp	ARM64: use 32-bit moves for constants where possible.	2014-04-16 11:52:51 +00:00
ARM64ExpandPseudoInsts.cpp
ARM64FastISel.cpp	Replacing a non-ASCII character in a comment with an ASCII character. Fixes a C4819 warning in MSVC.	2014-04-16 17:09:20 +00:00
ARM64FrameLowering.cpp
ARM64FrameLowering.h
ARM64InstrAtomics.td	ARM64: switch to IR-based atomic operations.	2014-04-17 20:00:33 +00:00
ARM64InstrFormats.td	AArch64/ARM64: add half as a storage type on ARM64.	2014-04-15 14:00:03 +00:00
ARM64InstrInfo.cpp	AArch64/ARM64: enable directcond.ll test on ARM64.	2014-04-14 12:51:06 +00:00
ARM64InstrInfo.h
ARM64InstrInfo.td	ARM64: implement cunning optimisation from AArch64	2014-04-18 09:31:20 +00:00
ARM64ISelDAGToDAG.cpp	ARM64: switch to IR-based atomic operations.	2014-04-17 20:00:33 +00:00
ARM64ISelLowering.cpp	ARM64: spot a vector_shuffle that maps to INS and expand.	2014-04-18 09:31:15 +00:00
ARM64ISelLowering.h	AArch64/ARM64: port BSL logic from AArch64 & enable test.	2014-04-18 09:31:01 +00:00
ARM64LoadStoreOptimizer.cpp
ARM64MachineFunctionInfo.h
ARM64MCInstLower.cpp
ARM64MCInstLower.h
ARM64PerfectShuffle.h
ARM64PromoteConstant.cpp	[ARM64,C++11] Range'ify another loop.	2014-04-17 23:41:57 +00:00
ARM64RegisterInfo.cpp
ARM64RegisterInfo.h
ARM64RegisterInfo.td	AArch64/ARM64: add half as a storage type on ARM64.	2014-04-15 14:00:03 +00:00
ARM64SchedCyclone.td
ARM64Schedule.td
ARM64SelectionDAGInfo.cpp
ARM64SelectionDAGInfo.h
ARM64StorePairSuppress.cpp
ARM64Subtarget.cpp	[ARM64] Set default CPU to generic instead of cyclone.	2014-04-15 19:08:46 +00:00
ARM64Subtarget.h	[ARM64] Port over missing subtarget features, and CPU definitions from AArch64.	2014-04-14 17:38:00 +00:00
ARM64TargetMachine.cpp	ARM64: add acquire/release versions of the existing atomic intrinsics.	2014-04-17 20:00:24 +00:00
ARM64TargetMachine.h
ARM64TargetObjectFile.cpp
ARM64TargetObjectFile.h
ARM64TargetTransformInfo.cpp	[ARM64] Never hoist the shift value of a shift instruction.	2014-04-12 02:53:51 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile