Tim Northover 70b63374f2 ARM64: implement cunning optimisation from AArch64 ... A vector extract followed by a dup can become a single instruction even if the types don't match. AArch64 handled this in ISelLowering, but a few reasonably simple patterns can take care of it in TableGen, so that's where I've put it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206573 91177308-0d34-0410-b5e6-96231b3b80d8		2014-04-18 09:31:20 +00:00
..
Analysis	Revert "blockfreq: Rewrite BlockFrequencyInfoImpl"	2014-04-18 02:17:43 +00:00
Assembler
Bindings
Bitcode
BugPoint
CodeGen	ARM64: implement cunning optimisation from AArch64	2014-04-18 09:31:20 +00:00
DebugInfo
ExecutionEngine
Feature
FileCheck
Instrumentation	[asan] one more workaround for PR17409: don't do BB-level coverage instrumentation if there are more than N (=1500) basic blocks. This makes ASanCoverage work on libjpeg_turbo/jchuff.c used by Chrome, which has 1824 BBs	2014-04-18 08:02:42 +00:00
Integer
JitListener
Linker
LTO
MC	Updated test with register names following r206565.	2014-04-18 08:50:09 +00:00
Object
Other
TableGen
tools	tools: fix invalid printing, buffer overrun in llvm-readobj	2014-04-16 04:15:29 +00:00
Transforms	Add missing config file for newly added test case introduced by r206563.	2014-04-18 09:05:50 +00:00
Unit
Verifier
YAMLParser
.clang-format
CMakeLists.txt	[CMake] check-llvm: Include "bugpoint" in dependent list.	2014-03-04 16:13:30 +00:00
lit.cfg
lit.site.cfg.in
Makefile
Makefile.tests	Remove dead code from the makefile build system.	2013-07-25 20:25:31 +00:00
TestRunner.sh