Tim Northover 70b63374f2 ARM64: implement cunning optimisation from AArch64 ... A vector extract followed by a dup can become a single instruction even if the types don't match. AArch64 handled this in ISelLowering, but a few reasonably simple patterns can take care of it in TableGen, so that's where I've put it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206573 91177308-0d34-0410-b5e6-96231b3b80d8		2014-04-18 09:31:20 +00:00
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AArch64	AArch64/ARM64: emit all vector FP comparisons as such.	2014-04-18 09:31:07 +00:00
ARM	Make FastISel::SelectInstruction return before target specific fast-isel code	2014-04-15 21:30:06 +00:00
ARM64	ARM64: implement cunning optimisation from AArch64	2014-04-18 09:31:20 +00:00
CPP
Generic
Hexagon
Inputs
Mips	[mips] Add initial support for NaN2008 in the back-end.	2014-04-16 15:48:55 +00:00
MSP430	Mark FPB as a reserved register when needed.	2014-04-02 13:13:56 +00:00
NVPTX	[NVPTX] Add preliminary intrinsics and codegen support for textures/surfaces	2014-04-09 15:39:15 +00:00
PowerPC	[PowerPC] Fix rlwimi isel when mask is not constant	2014-04-13 17:10:58 +00:00
R600	R600/SI: Try to use scalar BFE.	2014-04-18 05:19:26 +00:00
SPARC
SystemZ	Reenable use of TBAA during CodeGen	2014-04-12 01:26:00 +00:00
Thumb	Make this test not match its own filename, when being run from a path that includes the string 'add'.	2014-04-15 22:29:32 +00:00
Thumb2	Move the segmented stack switch to a function attribute	2014-04-10 22:58:43 +00:00
X86	[stack protector] Make the StackProtector pass respect ssp-buffer-size.	2014-04-17 19:08:36 +00:00
XCore	Revert "blockfreq: Rewrite BlockFrequencyInfoImpl"	2014-04-18 02:17:43 +00:00