Quentin Colombet f847657767 [X86][fast-isel] Fix select lowering. ... The condition in selects is supposed to be i1. Make sure we are just reading the less significant bit of the 8 bits width value to match this constraint. <rdar://problem/15651765> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197712 91177308-0d34-0410-b5e6-96231b3b80d8		2013-12-19 18:32:04 +00:00
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AArch64	[AArch64 NEON]Implment loading vector constant form constant pool.	2013-12-18 06:26:04 +00:00
ARM	Unbreak ARM buildbots after r197653 by forcing the target triple on this test.	2013-12-19 18:14:42 +00:00
CPP	Begin adding docs and IR-level support for the inalloca attribute	2013-12-19 02:14:12 +00:00
Generic	Fix pr18235.	2013-12-13 16:05:32 +00:00
Hexagon	Debug Info: update testing cases to specify the debug info version number.	2013-11-22 21:49:45 +00:00
Inputs	Debug Info: update testing cases to specify the debug info version number.	2013-11-22 21:49:45 +00:00
Mips	Fix a problem with mips16 stubs when calls are transformed during	2013-12-18 23:57:48 +00:00
MSP430	Make sure SP is always aligned on a 2 byte boundary	2013-10-24 09:32:31 +00:00
NVPTX	[NVPTX] Fix off-by-one error when creating the VT list for an SDNode	2013-12-05 12:58:00 +00:00
PowerPC	One ppc32-darwin, a i64 inside a structure can have 32 bit alignment.	2013-12-18 14:35:37 +00:00
R600	Add REQUIRES:asserts to 3 tests in llvm/test/CodeGen/R600 added in r192212.	2013-12-19 10:41:12 +00:00
SPARC	[SPARCV9]: Adjust the resultant pointer of DYNAMIC_STACKALLOC with the stack BIAS on sparcV9.	2013-12-09 05:13:25 +00:00
SystemZ	Revert "Add -mcpu=z10 to SystemZ tests."	2013-12-18 23:04:37 +00:00
Thumb	Correctly handle the degenerated triple "thumb".	2013-12-18 21:29:44 +00:00
Thumb2	Enabling thumb2 mode used to force support for armv6t2. Replace this	2013-12-13 11:16:00 +00:00
X86	[X86][fast-isel] Fix select lowering.	2013-12-19 18:32:04 +00:00
XCore	XCore target: Make handling of large frames not dependent upon an FP.	2013-12-02 11:05:28 +00:00