llvm-6502/test/MC
Bill Schmidt 8c775a4e7b [PowerPC] Implement the vpopcnt instructions for POWER8
Patch by Kit Barton.

Add the vector population count instructions for byte, halfword, word,
and doubleword sizes.  There are two major changes here:

    PPCISelLowering.cpp: Make CTPOP legal for vector types.
    PPCRegisterInfo.td: Added v2i64 to the VRRC register
      definition. This is needed for the doubleword variations of the
      integer ops that were added in P8. 

Test Plan

Test the instruction vpcnt* encoding/decoding in ppc64-encoding-vmx.s

Test the generation of the vpopcnt instructions for various vector
data types.  When adding the v2i64 type to the Vector Register set, I
also needed to add the appropriate bit conversion patterns between
v2i64 and the existing vector types.  Testing for these conversions
were also added in the test case by passing a different vector type as
a parameter into the test functions.  There is also a run step that
will ensure the vpopcnt instructions are generated when the vsx
feature is disabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228046 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-03 21:58:23 +00:00
..
AArch64
ARM ARM: further correct .fpu directive handling 2015-01-30 19:35:18 +00:00
AsmParser
COFF Bring r226038 back. 2015-01-19 15:16:06 +00:00
Disassembler [PowerPC] Implement the vpopcnt instructions for POWER8 2015-02-03 21:58:23 +00:00
ELF Revert llvm/test/MC/ELF/noexec.s in r227074, "Fix a problem where the AArch64 ELF assembler was failing with" 2015-01-26 09:30:29 +00:00
Hexagon
MachO Add r224985 back with fixes. 2015-01-19 21:11:14 +00:00
Markup
Mips [mips] Manually replace JAL pseudo-instructions with their JALR equivalent, instead of using InstAlias. 2015-01-30 11:18:50 +00:00
PowerPC [PowerPC] Implement the vpopcnt instructions for POWER8 2015-02-03 21:58:23 +00:00
R600
Sparc
SystemZ
X86 [X86] Make fxsave64/fxrstor64/xsave64/xsrstor64/xsaveopt64 parseable in AT&T syntax. Also make them the default output. 2015-02-03 11:03:57 +00:00