llvm-6502/lib/Target/PowerPC
Chris Lattner 892afa9556 When rewriting the original call instruction, make sure to rewrite it to
call the right address.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18213 91177308-0d34-0410-b5e6-96231b3b80d8
2004-11-24 18:00:02 +00:00
..
.cvsignore
LICENSE.TXT
Makefile
PowerPC.td
PowerPCInstrInfo.h
PowerPCTargetMachine.h
PPC32.td
PPC32ISelSimple.cpp
PPC32JITInfo.h
PPC32RegisterInfo.td
PPC64.td
PPC64CodeEmitter.cpp
PPC64InstrInfo.cpp
PPC64InstrInfo.h
PPC64ISelSimple.cpp
PPC64JITInfo.h
PPC64RegisterInfo.cpp
PPC64RegisterInfo.h
PPC64RegisterInfo.td
PPC64TargetMachine.h
PPC.h
PPCAsmPrinter.cpp
PPCBranchSelector.cpp
PPCCodeEmitter.cpp Loads are relocatable too 2004-11-24 02:03:44 +00:00
PPCFrameInfo.h
PPCInstrBuilder.h
PPCInstrFormats.td Fix a few more tests by encoding the extsb and other XForm11 instructions 2004-11-24 03:52:02 +00:00
PPCInstrInfo.cpp
PPCInstrInfo.h
PPCInstrInfo.td Fix encoding of bctrl, and remove some unused instructions 2004-11-24 00:16:37 +00:00
PPCJITInfo.cpp When rewriting the original call instruction, make sure to rewrite it to 2004-11-24 18:00:02 +00:00
PPCJITInfo.h
PPCRegisterInfo.cpp
PPCRegisterInfo.h
PPCRegisterInfo.td
PPCRelocations.h
PPCTargetMachine.cpp
PPCTargetMachine.h
README.txt

TODO:
* poor switch statement codegen
* load/store to alloca'd array or struct.
* implement not-R0 register GPR class
* implement scheduling info
* implement do-loop pass
* implement do-loop -> bdnz transform
* implement powerpc-64 for darwin
* implement powerpc-64 for aix
* use stfiwx in float->int
* should hint to the branch select pass that it doesn't need to print the
  second unconditional branch, so we don't end up with things like:
	b .LBBl42__2E_expand_function_8_674	; loopentry.24
	b .LBBl42__2E_expand_function_8_42	; NewDefault
	b .LBBl42__2E_expand_function_8_42	; NewDefault

Currently failing tests that should pass:
* MultiSource
  |- Applications
  |  `- hbd: miscompilation