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02d937d864
* lib/Target/Hexagon/HexagonInstrInfo.td: Add patterns to combine a sequence of a pair of i32->i64 extensions followed by a "bitwise or" into COMBINE_rr. * lib/Target/Hexagon/HexagonPeephole.cpp: Copy propagate Rx in the instruction Rp = COMBINE_Ir_V4(0, Rx) to the uses of Rp:subreg_loreg. * test/CodeGen/Hexagon/union-1.ll: New test. * test/CodeGen/Hexagon/combine_ir.ll: Fix test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180946 91177308-0d34-0410-b5e6-96231b3b80d8 |
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.. | ||
absaddr-store.ll | ||
absimm.ll | ||
adde.ll | ||
always-ext.ll | ||
args.ll | ||
ashift-left-right.ll | ||
block-addr.ll | ||
cext-check.ll | ||
cext-valid-packet1.ll | ||
cext-valid-packet2.ll | ||
cmp_pred2.ll | ||
cmp_pred_reg.ll | ||
cmp_pred.ll | ||
cmp-to-genreg.ll | ||
cmp-to-predreg.ll | ||
cmpb_pred.ll | ||
combine_ir.ll | ||
combine.ll | ||
convertdptoint.ll | ||
convertdptoll.ll | ||
convertsptoint.ll | ||
convertsptoll.ll | ||
ctlz-cttz-ctpop.ll | ||
dadd.ll | ||
dmul.ll | ||
double.ll | ||
doubleconvert-ieee-rnd-near.ll | ||
dsub.ll | ||
dualstore.ll | ||
fadd.ll | ||
fcmp.ll | ||
float.ll | ||
floatconvert-ieee-rnd-near.ll | ||
fmul.ll | ||
frame.ll | ||
fsub.ll | ||
fusedandshift.ll | ||
gp-plus-offset-load.ll | ||
gp-plus-offset-store.ll | ||
gp-rel.ll | ||
hwloop-cleanup.ll | ||
hwloop-const.ll | ||
hwloop-dbg.ll | ||
hwloop-le.ll | ||
hwloop-lt1.ll | ||
hwloop-lt.ll | ||
hwloop-ne.ll | ||
i1_VarArg.ll | ||
i8_VarArg.ll | ||
i16_VarArg.ll | ||
idxload-with-zero-offset.ll | ||
indirect-br.ll | ||
lit.local.cfg | ||
macint.ll | ||
memops1.ll | ||
memops2.ll | ||
memops3.ll | ||
memops.ll | ||
misaligned-access.ll | ||
mpy.ll | ||
newvaluejump2.ll | ||
newvaluejump.ll | ||
newvaluestore.ll | ||
opt-fabs.ll | ||
opt-fneg.ll | ||
postinc-load.ll | ||
postinc-store.ll | ||
pred-absolute-store.ll | ||
predicate-copy.ll | ||
remove_lsr.ll | ||
simpletailcall.ll | ||
static.ll | ||
struct_args_large.ll | ||
struct_args.ll | ||
sube.ll | ||
union-1.ll | ||
vaddh.ll | ||
validate-offset.ll | ||
zextloadi1.ll |