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92811fa2c7
llvm-6502/lib/Target/R600
History
Tom Stellard 92811fa2c7 R600/SI: Add 32-bit encoding of v_cndmask_b32 
This was done by refactoring the v_cndmask_b32 tablegen definition
to use inherit from VOP2Inst.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231795 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 16:16:44 +00:00
..
AsmParser
InstPrinter R600/SI: Move gds operand to the end of operand list 2015-03-09 18:49:54 +00:00
MCTargetDesc TableGen: Use 'enum : uint64_t' for feature flags to fix -Wmicrosoft 2015-03-09 20:23:14 +00:00
TargetInfo
AMDGPU.h
AMDGPU.td R600/SI: Limit SGPRs to 80 on Tonga and Iceland 2015-03-09 15:48:09 +00:00
AMDGPUAlwaysInlinePass.cpp
AMDGPUAsmPrinter.cpp R600/SI: Limit SGPRs to 80 on Tonga and Iceland 2015-03-09 15:48:09 +00:00
AMDGPUAsmPrinter.h Remove the DisasmEnabled AsmPrinter variable and just look it 2015-02-19 01:10:49 +00:00
AMDGPUCallingConv.td
AMDGPUFrameLowering.cpp
AMDGPUFrameLowering.h
AMDGPUInstrInfo.cpp ArrayRefize memory operand folding. NFC. 2015-02-28 12:04:00 +00:00
AMDGPUInstrInfo.h ArrayRefize memory operand folding. NFC. 2015-02-28 12:04:00 +00:00
AMDGPUInstrInfo.td R600: Use new fmad node. 2015-02-20 22:10:41 +00:00
AMDGPUInstructions.td R600: Use new fmad node. 2015-02-20 22:10:41 +00:00
AMDGPUIntrinsicInfo.cpp
AMDGPUIntrinsicInfo.h
AMDGPUIntrinsics.td R600/SI: Add an intrinsic for S_FLBIT_I32 / V_FFBH_I32 2015-03-04 17:33:45 +00:00
AMDGPUISelDAGToDAG.cpp R600/SI: Add slc, glc, and tfe to non-atomic _ADDR64 instructions 2015-02-27 14:59:41 +00:00
AMDGPUISelLowering.cpp R600/SI: Remove v_sub_f64 pseudo 2015-02-20 22:10:45 +00:00
AMDGPUISelLowering.h R600: Use new fmad node. 2015-02-20 22:10:41 +00:00
AMDGPUMachineFunction.cpp
AMDGPUMachineFunction.h
AMDGPUMCInstLower.cpp Grab the subtarget off of the machine function for the R600 2015-02-19 01:10:53 +00:00
AMDGPUMCInstLower.h
AMDGPUPromoteAlloca.cpp Make DataLayout Non-Optional in the Module 2015-03-04 18:43:29 +00:00
AMDGPURegisterInfo.cpp
AMDGPURegisterInfo.h
AMDGPURegisterInfo.td
AMDGPUSubtarget.cpp R600/SI: Limit SGPRs to 80 on Tonga and Iceland 2015-03-09 15:48:09 +00:00
AMDGPUSubtarget.h R600/SI: Limit SGPRs to 80 on Tonga and Iceland 2015-03-09 15:48:09 +00:00
AMDGPUTargetMachine.cpp
AMDGPUTargetMachine.h
AMDGPUTargetTransformInfo.cpp DataLayout is mandatory, update the API to reflect it with references. 2015-03-10 02:37:25 +00:00
AMDGPUTargetTransformInfo.h
AMDILCFGStructurizer.cpp
AMDKernelCodeT.h
CaymanInstructions.td R600/SI: Implement correct f64 fdiv 2015-02-14 04:30:08 +00:00
CIInstructions.td
CMakeLists.txt
EvergreenInstructions.td R600/SI: Implement correct f64 fdiv 2015-02-14 04:30:08 +00:00
LLVMBuild.txt
Makefile
Processors.td R600/SI: Limit SGPRs to 80 on Tonga and Iceland 2015-03-09 15:48:09 +00:00
R600ClauseMergePass.cpp
R600ControlFlowFinalizer.cpp
R600Defines.h
R600EmitClauseMarkers.cpp
R600ExpandSpecialInstrs.cpp
R600InstrFormats.td
R600InstrInfo.cpp R600: Use c++11 style for loop 2015-03-02 18:56:52 +00:00
R600InstrInfo.h
R600Instructions.td R600: Use new fmad node. 2015-02-20 22:10:41 +00:00
R600Intrinsics.td
R600ISelLowering.cpp DataLayout is mandatory, update the API to reflect it with references. 2015-03-10 02:37:25 +00:00
R600ISelLowering.h
R600MachineFunctionInfo.cpp
R600MachineFunctionInfo.h
R600MachineScheduler.cpp Remove a few more calls to TargetMachine::getSubtarget from the 2015-02-19 01:10:55 +00:00
R600MachineScheduler.h
R600OptimizeVectorRegisters.cpp
R600Packetizer.cpp
R600RegisterInfo.cpp
R600RegisterInfo.h
R600RegisterInfo.td
R600Schedule.td
R600TextureIntrinsicsReplacer.cpp
R700Instructions.td
SIAnnotateControlFlow.cpp
SIDefines.h
SIFixSGPRCopies.cpp
SIFixSGPRLiveRanges.cpp
SIFoldOperands.cpp R600/SI: Fix asam errors in SIFoldOperands 2015-02-17 20:11:54 +00:00
SIInsertWaits.cpp
SIInstrFormats.td R600/SI: Refactor DS instruction defs 2015-03-09 18:49:45 +00:00
SIInstrInfo.cpp R600/SI: Add an intrinsic for S_FLBIT_I32 / V_FFBH_I32 2015-03-04 17:33:45 +00:00
SIInstrInfo.h R600/SI: Try to use v_madak_f32 2015-02-21 21:29:07 +00:00
SIInstrInfo.td R600/SI: Add 32-bit encoding of v_cndmask_b32 2015-03-10 16:16:44 +00:00
SIInstructions.td R600/SI: Add 32-bit encoding of v_cndmask_b32 2015-03-10 16:16:44 +00:00
SIIntrinsics.td
SIISelLowering.cpp Make constant arrays that are passed to functions as const. 2015-03-07 17:41:00 +00:00
SIISelLowering.h R600/SI: Remove isel mubuf legalization 2015-02-24 17:59:19 +00:00
SILoadStoreOptimizer.cpp R600/SI: Move gds operand to the end of operand list 2015-03-09 18:49:54 +00:00
SILowerControlFlow.cpp
SILowerI1Copies.cpp
SIMachineFunctionInfo.cpp Remove a few more calls to TargetMachine::getSubtarget from the 2015-02-19 01:10:55 +00:00
SIMachineFunctionInfo.h
SIPrepareScratchRegs.cpp
SIRegisterInfo.cpp R600/SI: Limit SGPRs to 80 on Tonga and Iceland 2015-03-09 15:48:09 +00:00
SIRegisterInfo.h R600/SI: Fix getNumSGPRsAllowed for VI 2015-03-09 15:48:00 +00:00
SIRegisterInfo.td R600/SI: Remove unused register class 2015-03-06 17:00:16 +00:00
SISchedule.td
SIShrinkInstructions.cpp R600/SI: Add 32-bit encoding of v_cndmask_b32 2015-03-10 16:16:44 +00:00
SITypeRewriter.cpp
VIInstrFormats.td R600/SI: Rename dst encoding field to be consistent with docs 2015-02-18 02:15:37 +00:00
VIInstructions.td