Petr Pavlu ec223f1217 [AArch64] Fix problems in decoding generic MSR instructions ... Bitpatterns rejected by the decoder method of `MSR (immediate)` should be decoded as the `extended MSR (register)` instruction. Differential Revision: http://reviews.llvm.org/D7174 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242276 91177308-0d34-0410-b5e6-96231b3b80d8		2015-07-15 08:10:30 +00:00
..
a64-ignored-fields.txt
arm64-advsimd.txt	[AArch64] Allow non-standard INS/DUP encodings	2015-04-14 15:07:26 +00:00
arm64-arithmetic.txt
arm64-basic-a64-undefined.txt
arm64-bitfield.txt
arm64-branch.txt
arm64-canonical-form.txt
arm64-crc32.txt
arm64-crypto.txt
arm64-invalid-logical.txt
arm64-logical.txt
arm64-memory.txt
arm64-non-apple-fmov.txt
arm64-scalar-fp.txt
arm64-system.txt
armv8.1a-atomic.txt	AArch64: fix typo in SMIN far atomics and add tests	2015-06-02 18:37:20 +00:00
armv8.1a-lor.txt	[AArch64] LORID_EL1 register must be treated as read-only	2015-04-20 16:54:37 +00:00
armv8.1a-pan.txt	[AArch64] Add v8.1a "Privileged Access Never" extension	2015-04-16 15:20:51 +00:00
armv8.1a-rdma.txt	[AArch64] Add v8.1a "Rounding Double Multiply Add/Subtract" extension	2015-03-31 13:15:48 +00:00
armv8.1a-vhe.txt	[AArch64] Add v8.1a "Virtualization Host Extensions"	2015-04-16 15:38:58 +00:00
basic-a64-instructions.txt	[AArch64] Fix problems in decoding generic MSR instructions	2015-07-15 08:10:30 +00:00
basic-a64-undefined.txt
basic-a64-unpredictable.txt
gicv3-regs.txt
ldp-offset-predictable.txt
ldp-postind.predictable.txt
ldp-preind.predictable.txt
lit.local.cfg
neon-instructions.txt
trace-regs.txt