llvm-6502/lib/Target/Sparc
Brian Gaeke 6713d988a4 Make storeRegToStackSlot slightly shorter.
Make copyRegToReg return 1 instead of -1.
Edit a comment in emitPrologue().


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14211 91177308-0d34-0410-b5e6-96231b3b80d8
2004-06-17 22:34:48 +00:00
..
DelaySlotFiller.cpp Recognize more branches. 2004-06-17 22:33:57 +00:00
InstSelectSimple.cpp Support generating machine instructions for Phi nodes (based on x86, but with 2004-06-17 22:34:08 +00:00
Makefile Clean up rules 2004-02-28 19:43:40 +00:00
README.txt SparcV8 skeleton 2004-02-25 19:28:19 +00:00
Sparc.h Add references to delay slot filler pass. 2004-04-06 23:21:24 +00:00
Sparc.td Delete reference to "the Mach-O Runtime ABI". 2004-04-06 22:09:59 +00:00
SparcAsmPrinter.cpp Emit stores correctly; don't fail an assertion. 2004-06-17 22:34:19 +00:00
SparcInstrInfo.cpp Adjust to change in TII ctor arguments 2004-02-29 06:31:44 +00:00
SparcInstrInfo.h These two virtual methods are never called. 2004-02-29 05:59:33 +00:00
SparcInstrInfo.td Set the isBranch and isTerminator flags on branch instructions correctly. 2004-06-17 22:34:29 +00:00
SparcRegisterInfo.cpp Make storeRegToStackSlot slightly shorter. 2004-06-17 22:34:48 +00:00
SparcRegisterInfo.h SparcV8 skeleton 2004-02-25 19:28:19 +00:00
SparcRegisterInfo.td Merge my changes with brians 2004-04-07 04:05:49 +00:00
SparcTargetMachine.cpp I think we'll use the standard lowering passes for now. 2004-06-15 20:37:12 +00:00
SparcTargetMachine.h Adjust to new TM interfaces 2004-06-02 05:47:26 +00:00
SparcV8CodeEmitter.cpp SparcV8 skeleton 2004-02-25 19:28:19 +00:00
SparcV8InstrInfo_F2.td Tab completion is our friend. 2004-02-28 19:45:39 +00:00
SparcV8InstrInfo_F3.td Tab completion is our friend. 2004-02-28 19:45:39 +00:00
SparcV8ISelSimple.cpp Support generating machine instructions for Phi nodes (based on x86, but with 2004-06-17 22:34:08 +00:00
SparcV8JITInfo.h SparcV8 skeleton 2004-02-25 19:28:19 +00:00

SparcV8 backend skeleton
------------------------

This directory will house a 32-bit SPARC V8 backend employing a expander-based
instruction selector.  Watch this space for more news coming soon!

$Date$