llvm-6502/lib/CodeGen
2012-07-15 20:39:08 +00:00
..
AsmPrinter The end of the prologue should be marked with is_stmt. 2012-07-12 23:30:25 +00:00
SelectionDAG Fix a bug in the scalarization of BUILD_VECTOR. BUILD_VECTOR elements may be wider than the output element type. Make sure to trunc them if needed. 2012-07-15 20:39:08 +00:00
AggressiveAntiDepBreaker.cpp Move RegisterClassInfo.h. 2012-06-06 20:29:31 +00:00
AggressiveAntiDepBreaker.h
AllocationOrder.cpp Move RegisterClassInfo.h. 2012-06-06 20:29:31 +00:00
AllocationOrder.h
Analysis.cpp quick fix for PR13006, will check in testcase later. 2012-06-01 15:02:52 +00:00
AntiDepBreaker.h
BranchFolding.cpp Fix typos found by http://github.com/lyda/misspell-check 2012-06-02 10:20:22 +00:00
BranchFolding.h
CalcSpillWeights.cpp Avoid iterating with LiveIntervals::iterator. 2012-06-20 21:25:05 +00:00
CallingConvLower.cpp Add an ensureMaxAlignment() function to MachineFrameInfo (analogous to 2012-06-19 22:59:12 +00:00
CMakeLists.txt Add an experimental early if-conversion pass, off by default. 2012-07-04 00:09:54 +00:00
CodeGen.cpp Add an experimental early if-conversion pass, off by default. 2012-07-04 00:09:54 +00:00
CodePlacementOpt.cpp Fix typos found by http://github.com/lyda/misspell-check 2012-06-02 10:20:22 +00:00
CriticalAntiDepBreaker.cpp Fix typos found by http://github.com/lyda/misspell-check 2012-06-02 10:20:22 +00:00
CriticalAntiDepBreaker.h Move RegisterClassInfo.h. 2012-06-06 20:29:31 +00:00
DeadMachineInstructionElim.cpp Switch all register list clients to the new MC*Iterator interface. 2012-06-01 23:28:30 +00:00
DFAPacketizer.cpp Revert r158679 - use case is unclear (and it increases the memory footprint). 2012-06-22 20:27:13 +00:00
DwarfEHPrepare.cpp Relax the requirement that the exception object must be an instruction. During 2012-05-17 17:59:51 +00:00
EarlyIfConversion.cpp Require and preserve LoopInfo for early if-conversion. 2012-07-10 22:39:56 +00:00
EdgeBundles.cpp
ExecutionDepsFix.cpp Fix typos found by http://github.com/lyda/misspell-check 2012-06-02 10:20:22 +00:00
ExpandISelPseudos.cpp
ExpandPostRAPseudos.cpp
GCMetadata.cpp
GCMetadataPrinter.cpp
GCStrategy.cpp
IfConversion.cpp Start implementing pre-ra if-converter: using speculation and selects to eliminate branches. 2012-06-08 21:53:50 +00:00
InlineSpiller.cpp Account for early-clobber reload instructions. 2012-07-14 18:45:35 +00:00
InterferenceCache.cpp Convert RAGreedy to LiveRegMatrix interference checking. 2012-06-20 22:52:26 +00:00
InterferenceCache.h Convert RAGreedy to LiveRegMatrix interference checking. 2012-06-20 22:52:26 +00:00
IntrinsicLowering.cpp Move llvm/Support/IRBuilder.h -> llvm/IRBuilder.h 2012-06-29 12:38:19 +00:00
JITCodeEmitter.cpp
LatencyPriorityQueue.cpp
LexicalScopes.cpp Move lib/Analysis/DebugInfo.cpp to lib/VMCore/DebugInfo.cpp and 2012-06-28 00:05:13 +00:00
LiveDebugVariables.cpp Move lib/Analysis/DebugInfo.cpp to lib/VMCore/DebugInfo.cpp and 2012-06-28 00:05:13 +00:00
LiveDebugVariables.h
LiveInterval.cpp Teach the LiveInterval::join function to use the fast merge algorithm, 2012-07-10 22:25:21 +00:00
LiveIntervalAnalysis.cpp Delete a boring statistic. 2012-06-22 20:40:15 +00:00
LiveIntervalUnion.cpp Move LiveUnionArray into LiveIntervalUnion.h 2012-06-05 23:57:30 +00:00
LiveIntervalUnion.h Move LiveUnionArray into LiveIntervalUnion.h 2012-06-05 23:57:30 +00:00
LiveRangeCalc.cpp Be more verbose when detecting dominance problems. 2012-07-13 23:39:05 +00:00
LiveRangeCalc.h Be more verbose when detecting dominance problems. 2012-07-13 23:39:05 +00:00
LiveRangeEdit.cpp Use MRI::isConstantPhysReg() to check remat feasibility. 2012-06-22 17:31:01 +00:00
LiveRegMatrix.cpp Accept null PhysReg arguments to checkRegMaskInterference. 2012-06-15 22:24:22 +00:00
LiveRegMatrix.h Convert RAGreedy to LiveRegMatrix interference checking. 2012-06-20 22:52:26 +00:00
LiveStackAnalysis.cpp
LiveVariables.cpp Teach LiveVariables to handle <undef> operands. 2012-06-23 02:23:00 +00:00
LLVMBuild.txt
LLVMTargetMachine.cpp Extend TargetPassConfig to allow running only a subset of the normal passes. 2012-07-02 19:48:45 +00:00
LocalStackSlotAllocation.cpp Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass(). 2012-05-07 22:10:26 +00:00
MachineBasicBlock.cpp Remove assignments which aren't used afterwards. 2012-06-15 19:30:42 +00:00
MachineBlockFrequencyInfo.cpp
MachineBlockPlacement.cpp Update a bunch of stale comments that dated from when this folled the 2012-06-26 05:16:37 +00:00
MachineBranchProbabilityInfo.cpp
MachineCodeEmitter.cpp
MachineCopyPropagation.cpp Switch all register list clients to the new MC*Iterator interface. 2012-06-01 23:28:30 +00:00
MachineCSE.cpp Remove ParentMap. You can just ask the domnode for its parent. No functionality 2012-07-05 06:19:21 +00:00
MachineDominators.cpp
MachineFunction.cpp Move lib/Analysis/DebugInfo.cpp to lib/VMCore/DebugInfo.cpp and 2012-06-28 00:05:13 +00:00
MachineFunctionAnalysis.cpp
MachineFunctionPass.cpp
MachineFunctionPrinterPass.cpp Print SlotIndexes when available for -print-machineinstrs. 2012-07-04 23:53:19 +00:00
MachineInstr.cpp Finish fixing the MachineOperand hashing, providing a nice modern 2012-07-05 11:06:22 +00:00
MachineInstrBundle.cpp Switch all register list clients to the new MC*Iterator interface. 2012-06-01 23:28:30 +00:00
MachineLICM.cpp Switch all register list clients to the new MC*Iterator interface. 2012-06-01 23:28:30 +00:00
MachineLoopInfo.cpp Enable the new LoopInfo algorithm by default. 2012-06-26 04:11:38 +00:00
MachineLoopRanges.cpp
MachineModuleInfo.cpp
MachineModuleInfoImpls.cpp
MachinePassRegistry.cpp Allow targets to select the default scheduler by name. 2012-04-19 01:34:10 +00:00
MachineRegisterInfo.cpp Added assertion in getVRegDef of MachineRegisterInfo to make sure the virtual 2012-07-02 18:55:36 +00:00
MachineScheduler.cpp I'm introducing a new machine model to simultaneously allow simple 2012-07-07 04:00:00 +00:00
MachineSink.cpp
MachineSSAUpdater.cpp Fix two rather subtle internal vs. external linker issues. 2012-06-20 08:39:30 +00:00
MachineVerifier.cpp Check for extra kill flags on live-out virtual registers. 2012-06-29 21:00:00 +00:00
Makefile
OcamlGC.cpp
OptimizePHIs.cpp
Passes.cpp Make sure -print-machineinstrs applies to the first pass as well. 2012-07-04 19:28:27 +00:00
PeepholeOptimizer.cpp Add SrcReg2 to analyzeCompare and optimizeCompareInstr to handle Compare 2012-06-29 21:33:59 +00:00
PHIElimination.cpp Allow multiple terminators to read virtual registers. 2012-07-04 19:52:05 +00:00
PHIEliminationUtils.cpp
PHIEliminationUtils.h
PostRASchedulerList.cpp Move RegisterClassInfo.h. 2012-06-06 20:29:31 +00:00
ProcessImplicitDefs.cpp Run ProcessImplicitDefs on SSA form where it can be much simpler. 2012-06-25 18:12:18 +00:00
PrologEpilogInserter.cpp Remove extra space. 2012-05-30 18:47:55 +00:00
PrologEpilogInserter.h
PseudoSourceValue.cpp
README.txt
RegAllocBase.cpp Remove LiveIntervalUnions from RegAllocBase. 2012-06-20 22:52:29 +00:00
RegAllocBase.h Remove LiveIntervalUnions from RegAllocBase. 2012-06-20 22:52:29 +00:00
RegAllocBasic.cpp Remove the RenderMachineFunction HTML output pass. 2012-06-20 23:47:58 +00:00
RegAllocFast.cpp Move RegisterClassInfo.h. 2012-06-06 20:29:31 +00:00
RegAllocGreedy.cpp Remove LiveIntervalUnions from RegAllocBase. 2012-06-20 22:52:29 +00:00
RegAllocPBQP.cpp Remove LiveIntervals::trackingRegUnits(). 2012-06-22 16:46:44 +00:00
RegisterClassInfo.cpp Move RegisterClassInfo.h. 2012-06-06 20:29:31 +00:00
RegisterCoalescer.cpp Now that RegistersDefinedFromSameValue handles one instruction being an 2012-07-01 17:08:01 +00:00
RegisterCoalescer.h Remove unused private fields found by clang's new -Wunused-private-field. 2012-06-06 18:25:08 +00:00
RegisterPressure.cpp misched: When querying RegisterPressureTracker, always save current and max pressure. 2012-06-11 23:42:23 +00:00
RegisterScavenging.cpp Switch all register list clients to the new MC*Iterator interface. 2012-06-01 23:28:30 +00:00
ScheduleDAG.cpp sched: Avoid trivially redundant DAG edges. Take the one with higher latency. 2012-06-13 02:39:00 +00:00
ScheduleDAGInstrs.cpp misched: disable SSA check pending PR13112. 2012-06-14 17:48:49 +00:00
ScheduleDAGPrinter.cpp
ScoreboardHazardRecognizer.cpp I'm introducing a new machine model to simultaneously allow simple 2012-07-07 04:00:00 +00:00
ShadowStackGC.cpp Move llvm/Support/IRBuilder.h -> llvm/IRBuilder.h 2012-06-29 12:38:19 +00:00
ShrinkWrapping.cpp
SjLjEHPrepare.cpp Move llvm/Support/IRBuilder.h -> llvm/IRBuilder.h 2012-06-29 12:38:19 +00:00
SlotIndexes.cpp Remove more dead code. 2012-04-25 18:01:30 +00:00
Spiller.cpp Moved LiveRangeEdit.h so that it can be called from other parts of the backend, not just libCodeGen 2012-04-02 22:44:18 +00:00
Spiller.h
SpillPlacement.cpp Give a small negative bias to giant edge bundles. 2012-05-21 03:11:23 +00:00
SpillPlacement.h
SplitKit.cpp Pass context pointers to LiveRangeCalc::reset(). 2012-06-04 18:21:16 +00:00
SplitKit.h
StackProtector.cpp
StackSlotColoring.cpp
StrongPHIElimination.cpp
TailDuplication.cpp Stop leaking RegScavengers from TailDuplication. 2012-06-06 13:53:41 +00:00
TargetFrameLoweringImpl.cpp
TargetInstrInfoImpl.cpp indentation 2012-07-09 20:43:01 +00:00
TargetLoweringObjectFileImpl.cpp Move the support for using .init_array from ARM to the generic 2012-06-19 00:48:28 +00:00
TargetOptionsImpl.cpp
TwoAddressInstructionPass.cpp Reapply r160194, switching to use LV information for finding local kills. 2012-07-15 03:29:46 +00:00
UnreachableBlockElim.cpp
VirtRegMap.cpp Also compute MBB live-in lists in the new rewriter pass. 2012-06-09 00:14:47 +00:00
VirtRegMap.h Reintroduce VirtRegRewriter. 2012-06-08 23:44:45 +00:00

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelihood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvements:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.