llvm-6502/lib/CodeGen
Ulrich Weigand b64e2115de Do not consider a machine instruction that uses and defines the same
physical register as candidate for common subexpression elimination
in MachineCSE.

This fixes a bug on PowerPC in MultiSource/Applications/oggenc/oggenc
caused by MachineCSE invalidly merging two separate DYNALLOC insns.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167855 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13 18:40:58 +00:00
..
AsmPrinter Use the 'count' attribute instead of the 'upper_bound' attribute. 2012-11-13 02:31:47 +00:00
SelectionDAG Codegen support for arbitrary vector getelementptrs. 2012-11-13 13:01:58 +00:00
AggressiveAntiDepBreaker.cpp Remove RegisterClassInfo::isReserved() and isAllocatable(). 2012-10-15 22:41:03 +00:00
AggressiveAntiDepBreaker.h
AllocationOrder.cpp Remove RegisterClassInfo::isReserved() and isAllocatable(). 2012-10-15 22:41:03 +00:00
AllocationOrder.h
Analysis.cpp Move the Attributes::Builder outside of the Attributes class and into its own class named AttrBuilder. No functionality change. 2012-10-15 20:35:56 +00:00
AntiDepBreaker.h
BranchFolding.cpp Create enums for the different attributes. 2012-10-09 07:45:08 +00:00
BranchFolding.h
CalcSpillWeights.cpp Remove LIS::isAllocatable() and isReserved() helpers. 2012-10-15 22:14:34 +00:00
CallingConvLower.cpp Issue: 2012-10-16 07:16:47 +00:00
CMakeLists.txt Add a MachinePostDominator pass 2012-09-17 14:08:37 +00:00
CodeGen.cpp Add a MachinePostDominator pass 2012-09-17 14:08:37 +00:00
CodePlacementOpt.cpp Create enums for the different attributes. 2012-10-09 07:45:08 +00:00
CriticalAntiDepBreaker.cpp Remove RegisterClassInfo::isReserved() and isAllocatable(). 2012-10-15 22:41:03 +00:00
CriticalAntiDepBreaker.h Move RegisterClassInfo.h. 2012-06-06 20:29:31 +00:00
DeadMachineInstructionElim.cpp Switch most getReservedRegs() clients to the MRI equivalent. 2012-10-15 21:57:41 +00:00
DFAPacketizer.cpp Revert r158679 - use case is unclear (and it increases the memory footprint). 2012-06-22 20:27:13 +00:00
DwarfEHPrepare.cpp Relax the requirement that the exception object must be an instruction. During 2012-05-17 17:59:51 +00:00
EarlyIfConversion.cpp Stop running the machine code verifier unconditionally. 2012-10-25 00:05:39 +00:00
EdgeBundles.cpp
ExecutionDepsFix.cpp Merge MRI::isPhysRegOrOverlapUsed() into isPhysRegUsed(). 2012-10-17 18:44:18 +00:00
ExpandISelPseudos.cpp
ExpandPostRAPseudos.cpp Tidy up a few more uses of MF.getFunction()->getName(). 2012-08-22 17:18:53 +00:00
GCMetadata.cpp
GCMetadataPrinter.cpp
GCStrategy.cpp Remove GC roots that reference dead objects. 2012-10-26 09:15:55 +00:00
IfConversion.cpp Reduce duplicated hash map lookups. 2012-08-22 15:37:57 +00:00
InlineSpiller.cpp Add an analyzePhysReg() function to MachineOperandIteratorBase that analyses an instruction's use of a physical register, analogous to analyzeVirtReg. 2012-09-12 10:03:31 +00:00
InterferenceCache.cpp Convert RAGreedy to LiveRegMatrix interference checking. 2012-06-20 22:52:26 +00:00
InterferenceCache.h Convert RAGreedy to LiveRegMatrix interference checking. 2012-06-20 22:52:26 +00:00
IntrinsicLowering.cpp Revert the series of commits starting with r166578 which introduced the 2012-11-01 08:07:29 +00:00
JITCodeEmitter.cpp
LatencyPriorityQueue.cpp
LexicalScopes.cpp Move lib/Analysis/DebugInfo.cpp to lib/VMCore/DebugInfo.cpp and 2012-06-28 00:05:13 +00:00
LiveDebugVariables.cpp Tidy up a few more uses of MF.getFunction()->getName(). 2012-08-22 17:18:53 +00:00
LiveDebugVariables.h
LiveInterval.cpp Don't dereference begin() on an empty vector. 2012-09-27 21:05:59 +00:00
LiveIntervalAnalysis.cpp Fix assertions in updateRegMaskSlots(). 2012-11-09 19:18:49 +00:00
LiveIntervalUnion.cpp Move LiveUnionArray into LiveIntervalUnion.h 2012-06-05 23:57:30 +00:00
LiveIntervalUnion.h Use LLVM_DELETED_FUNCTION in place of 'DO NOT IMPLEMENT' comments. 2012-09-15 17:09:36 +00:00
LiveRangeCalc.cpp Clear kill flags while computing live ranges. 2012-09-06 18:15:15 +00:00
LiveRangeCalc.h Be more verbose when detecting dominance problems. 2012-07-13 23:39:05 +00:00
LiveRangeEdit.cpp Avoid rematerializing a redef immediately after the old def. 2012-10-16 22:51:58 +00:00
LiveRegMatrix.cpp Allow overlaps between virtreg and physreg live ranges. 2012-09-06 18:15:23 +00:00
LiveRegMatrix.h comment typo 2012-09-18 22:57:42 +00:00
LiveStackAnalysis.cpp Fix a significant recent(?) regression. StackSlotColoring no longer did anything 2012-09-21 20:04:28 +00:00
LiveVariables.cpp Switch most getReservedRegs() clients to the MRI equivalent. 2012-10-15 21:57:41 +00:00
LLVMBuild.txt
LLVMTargetMachine.cpp When creating MCAsmBackend pass the CPU string as well. In X86AsmBackend 2012-09-18 16:08:49 +00:00
LocalStackSlotAllocation.cpp Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass(). 2012-05-07 22:10:26 +00:00
MachineBasicBlock.cpp Make sure I is not the end iterator when isInsideBundle is called. 2012-10-26 17:11:42 +00:00
MachineBlockFrequencyInfo.cpp
MachineBlockPlacement.cpp Create enums for the different attributes. 2012-10-09 07:45:08 +00:00
MachineBranchProbabilityInfo.cpp Fix a quadratic algorithm in MachineBranchProbabilityInfo. 2012-08-20 22:01:38 +00:00
MachineCodeEmitter.cpp
MachineCopyPropagation.cpp Switch most getReservedRegs() clients to the MRI equivalent. 2012-10-15 21:57:41 +00:00
MachineCSE.cpp Do not consider a machine instruction that uses and defines the same 2012-11-13 18:40:58 +00:00
MachineDominators.cpp
MachineFunction.cpp Revert the majority of the next patch in the address space series: 2012-11-01 09:14:31 +00:00
MachineFunctionAnalysis.cpp
MachineFunctionPass.cpp
MachineFunctionPrinterPass.cpp Symbol hygiene: Make sure declarations and definitions match, make helper functions static. 2012-10-20 12:53:26 +00:00
MachineInstr.cpp Check that iterator I is not the end iterator. 2012-10-31 00:50:52 +00:00
MachineInstrBundle.cpp Increase the static sizes of some SmallSets. finalizeBundle() is very frequently called for some backends, and growing into an std::set is overkill for these numbers. 2012-09-17 18:31:15 +00:00
MachineLICM.cpp Add a getName function to MachineFunction. Use it in places that previously did getFunction()->getName(). Remove includes of Function.h that are no longer needed. 2012-08-22 06:07:19 +00:00
MachineLoopInfo.cpp Release build: guard dump functions with 2012-09-11 22:23:19 +00:00
MachineLoopRanges.cpp
MachineModuleInfo.cpp Move TargetData to DataLayout. 2012-10-08 16:38:25 +00:00
MachineModuleInfoImpls.cpp Rename virtual table anchors from Anchor() to anchor() for consistency with the rest of the tree. 2012-09-26 06:36:36 +00:00
MachinePassRegistry.cpp Allow targets to select the default scheduler by name. 2012-04-19 01:34:10 +00:00
MachinePostDominators.cpp Add a MachinePostDominator pass 2012-09-17 14:08:37 +00:00
MachineRegisterInfo.cpp Switch MRI::UsedPhysRegs to a register unit bit vector. 2012-10-17 20:26:33 +00:00
MachineScheduler.cpp misched: Allow subtargets to enable misched and dependent options. 2012-11-13 08:47:29 +00:00
MachineSink.cpp Remove unused BitVectors from getAllocatableSet(). 2012-10-16 00:05:06 +00:00
MachineSSAUpdater.cpp Fix undefined behavior: binding null pointer to reference. No functionality change. 2012-08-14 05:31:26 +00:00
MachineTraceMetrics.cpp Pass an explicit operand number to addLiveIns. 2012-10-11 16:46:07 +00:00
MachineTraceMetrics.h Pass an explicit operand number to addLiveIns. 2012-10-11 16:46:07 +00:00
MachineVerifier.cpp [inline asm] Implement mayLoad and mayStore for inline assembly. In general, 2012-10-30 19:11:54 +00:00
Makefile
OcamlGC.cpp
OptimizePHIs.cpp
Passes.cpp misched: Allow subtargets to enable misched and dependent options. 2012-11-13 08:47:29 +00:00
PeepholeOptimizer.cpp Make sure we iterate over newly created instructions. Fixes pr13625. Testcase to 2012-10-15 18:21:07 +00:00
PHIElimination.cpp Split loop exiting edges more aggressively. 2012-07-20 20:49:53 +00:00
PHIEliminationUtils.cpp
PHIEliminationUtils.h
PostRASchedulerList.cpp misched: Don't consider artificial edges weak edges. 2012-11-13 02:35:06 +00:00
ProcessImplicitDefs.cpp Tidy up a few more uses of MF.getFunction()->getName(). 2012-08-22 17:18:53 +00:00
PrologEpilogInserter.cpp Merge MRI::isPhysRegOrOverlapUsed() into isPhysRegUsed(). 2012-10-17 18:44:18 +00:00
PrologEpilogInserter.h
PseudoSourceValue.cpp
README.txt
RegAllocBase.cpp Remove LiveIntervalUnions from RegAllocBase. 2012-06-20 22:52:29 +00:00
RegAllocBase.h Remove LiveIntervalUnions from RegAllocBase. 2012-06-20 22:52:29 +00:00
RegAllocBasic.cpp Tidy up a few more uses of MF.getFunction()->getName(). 2012-08-22 17:18:53 +00:00
RegAllocFast.cpp [regallocfast] Make sure the MachineRegisterInfo is aware of clobbers from a 2012-11-06 22:52:42 +00:00
RegAllocGreedy.cpp Fix a significant recent(?) regression. StackSlotColoring no longer did anything 2012-09-21 20:04:28 +00:00
RegAllocPBQP.cpp Remove unused typedef. 2012-10-29 04:57:52 +00:00
RegisterClassInfo.cpp Switch most getReservedRegs() clients to the MRI equivalent. 2012-10-15 21:57:41 +00:00
RegisterCoalescer.cpp Fix -join-splitedges: my previous "cleanup" broke it. 2012-11-13 17:37:46 +00:00
RegisterCoalescer.h Allow overlaps between virtreg and physreg live ranges. 2012-09-06 18:15:23 +00:00
RegisterPressure.cpp misched: handle on-the-fly regpressure queries better for 2-addr 2012-11-07 07:05:05 +00:00
RegisterScavenging.cpp Switch most getReservedRegs() clients to the MRI equivalent. 2012-10-15 21:57:41 +00:00
ScheduleDAG.cpp misched: Don't consider artificial edges weak edges. 2012-11-13 02:35:06 +00:00
ScheduleDAGInstrs.cpp misched: Infrastructure for weak DAG edges. 2012-11-12 19:28:57 +00:00
ScheduleDAGPrinter.cpp Add a getName function to MachineFunction. Use it in places that previously did getFunction()->getName(). Remove includes of Function.h that are no longer needed. 2012-08-22 06:07:19 +00:00
ScoreboardHazardRecognizer.cpp Release build: guard dump functions with 2012-09-11 22:23:19 +00:00
ShadowStackGC.cpp Move llvm/Support/IRBuilder.h -> llvm/IRBuilder.h 2012-06-29 12:38:19 +00:00
ShrinkWrapping.cpp Add a getName function to MachineFunction. Use it in places that previously did getFunction()->getName(). Remove includes of Function.h that are no longer needed. 2012-08-22 06:07:19 +00:00
SjLjEHPrepare.cpp Move TargetData to DataLayout. 2012-10-08 16:38:25 +00:00
SlotIndexes.cpp Release build: guard dump functions with 2012-09-11 22:23:19 +00:00
Spiller.cpp Moved LiveRangeEdit.h so that it can be called from other parts of the backend, not just libCodeGen 2012-04-02 22:44:18 +00:00
Spiller.h
SpillPlacement.cpp Give a small negative bias to giant edge bundles. 2012-05-21 03:11:23 +00:00
SpillPlacement.h
SplitKit.cpp Release build: guard dump functions with 2012-09-11 22:23:19 +00:00
SplitKit.h
StackColoring.cpp Clear unknown mem ops when merging stack slots (pr14090) 2012-10-18 19:53:48 +00:00
StackProtector.cpp Create enums for the different attributes. 2012-10-09 07:45:08 +00:00
StackSlotColoring.cpp Fix a significant recent(?) regression. StackSlotColoring no longer did anything 2012-09-21 20:04:28 +00:00
StrongPHIElimination.cpp Reduce duplicated hash map lookups. 2012-08-22 15:37:57 +00:00
TailDuplication.cpp Create enums for the different attributes. 2012-10-09 07:45:08 +00:00
TargetFrameLoweringImpl.cpp
TargetInstrInfoImpl.cpp misched: Handle "transient" non-instructions. 2012-10-11 05:37:06 +00:00
TargetLoweringObjectFileImpl.cpp Revert the majority of the next patch in the address space series: 2012-11-01 09:14:31 +00:00
TargetOptionsImpl.cpp
TargetSchedule.cpp misched: TargetSchedule interface for machine resources. 2012-11-06 07:10:38 +00:00
TwoAddressInstructionPass.cpp Reduce indentation with early exit. 2012-10-26 23:05:13 +00:00
UnreachableBlockElim.cpp
VirtRegMap.cpp Switch most getReservedRegs() clients to the MRI equivalent. 2012-10-15 21:57:41 +00:00
VirtRegMap.h Use LLVM_DELETED_FUNCTION in place of 'DO NOT IMPLEMENT' comments. 2012-09-15 17:09:36 +00:00

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelihood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvements:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.