llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-16 11:30:51 +00:00

History

Reid Spencer b83eb6447b For PR950: This patch implements the first increment for the Signless Types feature. All changes pertain to removing the ConstantSInt and ConstantUInt classes in favor of just using ConstantInt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31063 91177308-0d34-0410-b5e6-96231b3b80d8		2006-10-20 07:07:24 +00:00
..
.cvsignore	Ignore generated files	2006-05-27 01:23:30 +00:00
ARM.h	Implement a MachineFunctionPass to fix the mul instruction	2006-09-19 15:49:25 +00:00
ARM.td	getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.	2006-05-18 00:12:58 +00:00
ARMAsmPrinter.cpp	print common symbols	2006-10-19 13:30:40 +00:00
ARMFrameInfo.h	use @ for comments	2006-08-25 17:55:16 +00:00
ARMInstrInfo.cpp	add shifts to addressing mode 1	2006-09-13 12:09:43 +00:00
ARMInstrInfo.h	change the addressing mode of the str instruction to reg+imm	2006-08-08 20:35:03 +00:00
ARMInstrInfo.td	use Pat to implement extloadi8 and extloadi16	2006-10-19 17:05:03 +00:00
ARMISelDAGToDAG.cpp	For PR950:	2006-10-20 07:07:24 +00:00
ARMMul.cpp	implement smull and umull	2006-10-16 16:33:29 +00:00
ARMRegisterInfo.cpp	add the immediate to the Offset in eliminateFrameIndex	2006-10-17 14:34:02 +00:00
ARMRegisterInfo.h	getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.	2006-05-18 00:12:58 +00:00
ARMRegisterInfo.td	fix the names of the 64bit fp register	2006-10-02 19:30:56 +00:00
ARMTargetAsmInfo.cpp	Break out target asm info into separate files.	2006-09-07 22:05:02 +00:00
ARMTargetAsmInfo.h	Break out target asm info into separate files.	2006-09-07 22:05:02 +00:00
ARMTargetMachine.cpp	most ARM targets are little endian	2006-10-09 14:12:15 +00:00
ARMTargetMachine.h	Implement a MachineFunctionPass to fix the mul instruction	2006-09-19 15:49:25 +00:00
Makefile	added a skeleton of the ARM backend	2006-05-14 22:18:28 +00:00
README.txt	add FSTD and FSTS	2006-10-17 13:36:07 +00:00

README.txt

//===---------------------------------------------------------------------===//
// Random ideas for the ARM backend.
//===---------------------------------------------------------------------===//

Consider implementing a select with two conditional moves:

cmp x, y
moveq dst, a
movne dst, b

----------------------------------------------------------


%tmp1 = shl int %b, ubyte %c
%tmp4 = add int %a, %tmp1

compiles to

add r0, r0, r1, lsl r2

but

%tmp1 = shl int %b, ubyte %c
%tmp4 = add int %tmp1, %a

compiles to
mov r1, r1, lsl r2
add r0, r1, r0

----------------------------------------------------------

add an offset to FLDS/FLDD/FSTD/FSTS addressing mode

----------------------------------------------------------

the function

void %f() {
entry:
	call void %g( int 1, int 2, int 3, int 4, int 5 )
	ret void
}

declare void %g(int, int, int, int, int)

Only needs 8 bytes of stack space. We currently allocate 16.

----------------------------------------------------------

32 x 32 -> 64 multiplications currently uses two instructions. We
should try to declare smull and umull as returning two values.

----------------------------------------------------------

Implement addressing modes 2 (ldrb) and 3 (ldrsb)

----------------------------------------------------------