| .. |
|
InstPrinter
|
|
|
|
MCTargetDesc
|
Remove unused stdio.h includes
|
2013-08-18 08:29:51 +00:00 |
|
TargetInfo
|
|
|
|
AMDGPU.h
|
R600/SI: Convert v16i8 resource descriptors to i128
|
2013-08-14 23:24:45 +00:00 |
|
AMDGPU.td
|
|
|
|
AMDGPUAsmPrinter.cpp
|
|
|
|
AMDGPUAsmPrinter.h
|
|
|
|
AMDGPUCallingConv.td
|
R600/SI: Fix an obvious typo
|
2013-08-14 22:22:03 +00:00 |
|
AMDGPUConvertToISA.cpp
|
|
|
|
AMDGPUFrameLowering.cpp
|
|
|
|
AMDGPUFrameLowering.h
|
|
|
|
AMDGPUIndirectAddressing.cpp
|
|
|
|
AMDGPUInstrInfo.cpp
|
|
|
|
AMDGPUInstrInfo.h
|
|
|
|
AMDGPUInstrInfo.td
|
R600: Add support for i16 and i8 global stores
|
2013-08-16 01:12:06 +00:00 |
|
AMDGPUInstructions.td
|
R600: Add support for i16 and i8 global stores
|
2013-08-16 01:12:06 +00:00 |
|
AMDGPUIntrinsics.td
|
|
|
|
AMDGPUISelDAGToDAG.cpp
|
R600: Enable folding of inline literals into REQ_SEQUENCE instructions
|
2013-08-16 01:11:55 +00:00 |
|
AMDGPUISelLowering.cpp
|
R600: Expand vector FRINT ops
|
2013-08-16 23:51:33 +00:00 |
|
AMDGPUISelLowering.h
|
R600: Add support for global vector stores with elements less than 32-bits
|
2013-08-16 01:12:11 +00:00 |
|
AMDGPUMachineFunction.cpp
|
|
|
|
AMDGPUMachineFunction.h
|
|
|
|
AMDGPUMCInstLower.cpp
|
|
|
|
AMDGPUMCInstLower.h
|
|
|
|
AMDGPURegisterInfo.cpp
|
R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2
|
2013-08-14 23:24:32 +00:00 |
|
AMDGPURegisterInfo.h
|
R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2
|
2013-08-14 23:24:32 +00:00 |
|
AMDGPURegisterInfo.td
|
|
|
|
AMDGPUSubtarget.cpp
|
Remove unused stdio.h includes
|
2013-08-18 08:29:51 +00:00 |
|
AMDGPUSubtarget.h
|
|
|
|
AMDGPUTargetMachine.cpp
|
R600/SI: Convert v16i8 resource descriptors to i128
|
2013-08-14 23:24:45 +00:00 |
|
AMDGPUTargetMachine.h
|
|
|
|
AMDGPUTargetTransformInfo.cpp
|
|
|
|
AMDILBase.td
|
|
|
|
AMDILCFGStructurizer.cpp
|
|
|
|
AMDILInstrInfo.td
|
|
|
|
AMDILIntrinsicInfo.cpp
|
|
|
|
AMDILIntrinsicInfo.h
|
|
|
|
AMDILIntrinsics.td
|
|
|
|
AMDILISelLowering.cpp
|
|
|
|
AMDILRegisterInfo.td
|
|
|
|
CMakeLists.txt
|
R600/SI: Convert v16i8 resource descriptors to i128
|
2013-08-14 23:24:45 +00:00 |
|
LLVMBuild.txt
|
|
|
|
Makefile
|
|
|
|
Processors.td
|
|
|
|
R600ControlFlowFinalizer.cpp
|
R600: Add IsExport bit to TableGen instruction definitions
|
2013-08-16 01:11:51 +00:00 |
|
R600Defines.h
|
R600: Add IsExport bit to TableGen instruction definitions
|
2013-08-16 01:11:51 +00:00 |
|
R600EmitClauseMarkers.cpp
|
|
|
|
R600ExpandSpecialInstrs.cpp
|
|
|
|
R600InstrFormats.td
|
R600: Add IsExport bit to TableGen instruction definitions
|
2013-08-16 01:11:51 +00:00 |
|
R600InstrInfo.cpp
|
R600: Add IsExport bit to TableGen instruction definitions
|
2013-08-16 01:11:51 +00:00 |
|
R600InstrInfo.h
|
R600: Add IsExport bit to TableGen instruction definitions
|
2013-08-16 01:11:51 +00:00 |
|
R600Instructions.td
|
R600: Add support for i16 and i8 global stores
|
2013-08-16 01:12:06 +00:00 |
|
R600Intrinsics.td
|
|
|
|
R600ISelLowering.cpp
|
R600: Expand vector float operations for both SI and R600
|
2013-08-16 23:51:24 +00:00 |
|
R600ISelLowering.h
|
|
|
|
R600MachineFunctionInfo.cpp
|
|
|
|
R600MachineFunctionInfo.h
|
|
|
|
R600MachineScheduler.cpp
|
Revert "R600: Non vector only instruction can be scheduled on trans unit"
|
2013-07-31 20:43:27 +00:00 |
|
R600MachineScheduler.h
|
Revert "R600: Non vector only instruction can be scheduled on trans unit"
|
2013-07-31 20:43:27 +00:00 |
|
R600OptimizeVectorRegisters.cpp
|
R600: Enable folding of inline literals into REQ_SEQUENCE instructions
|
2013-08-16 01:11:55 +00:00 |
|
R600Packetizer.cpp
|
Revert "R600: Non vector only instruction can be scheduled on trans unit"
|
2013-07-31 20:43:27 +00:00 |
|
R600RegisterInfo.cpp
|
R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2
|
2013-08-14 23:24:32 +00:00 |
|
R600RegisterInfo.h
|
R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2
|
2013-08-14 23:24:32 +00:00 |
|
R600RegisterInfo.td
|
R600: Add 64-bit float load/store support
|
2013-08-01 15:23:42 +00:00 |
|
R600Schedule.td
|
|
|
|
R600TextureIntrinsicsReplacer.cpp
|
R600: Fix possible use of an uninitialized variable
|
2013-08-17 00:06:51 +00:00 |
|
SIAnnotateControlFlow.cpp
|
|
|
|
SIDefines.h
|
R600/SI: Fix broken encoding of DS_WRITE_B32
|
2013-08-16 16:19:24 +00:00 |
|
SIFixSGPRCopies.cpp
|
R600/SI: Use VSrc_* register classes as the default classes for types
|
2013-08-06 23:08:28 +00:00 |
|
SIInsertWaits.cpp
|
R600/SI: Fix broken encoding of DS_WRITE_B32
|
2013-08-16 16:19:24 +00:00 |
|
SIInstrFormats.td
|
R600/SI: Fix broken encoding of DS_WRITE_B32
|
2013-08-16 16:19:24 +00:00 |
|
SIInstrInfo.cpp
|
Remove unused stdio.h includes
|
2013-08-18 08:29:51 +00:00 |
|
SIInstrInfo.h
|
R600/SI: Fix broken encoding of DS_WRITE_B32
|
2013-08-16 16:19:24 +00:00 |
|
SIInstrInfo.td
|
Revert "R600/SI: Fix incorrect encoding of DS_WRITE_B32 instructions"
|
2013-08-16 01:18:43 +00:00 |
|
SIInstructions.td
|
R600/SI: Add pattern for xor of i1
|
2013-08-16 16:19:31 +00:00 |
|
SIIntrinsics.td
|
R600/SI: Convert v16i8 resource descriptors to i128
|
2013-08-14 23:24:45 +00:00 |
|
SIISelLowering.cpp
|
R600: Allocate memoperand in the MachienFunction so it doesn't leak.
|
2013-08-16 14:48:09 +00:00 |
|
SIISelLowering.h
|
R600/SI: Improve legalization of vector operations
|
2013-08-14 23:25:00 +00:00 |
|
SILowerControlFlow.cpp
|
|
|
|
SIMachineFunctionInfo.cpp
|
|
|
|
SIMachineFunctionInfo.h
|
|
|
|
SIRegisterInfo.cpp
|
R600/SI: Choose the correct MOV instruction for copying immediates
|
2013-08-14 23:24:24 +00:00 |
|
SIRegisterInfo.h
|
R600/SI: Choose the correct MOV instruction for copying immediates
|
2013-08-14 23:24:24 +00:00 |
|
SIRegisterInfo.td
|
R600/SI: Convert v16i8 resource descriptors to i128
|
2013-08-14 23:24:45 +00:00 |
|
SISchedule.td
|
|
|
|
SITypeRewriter.cpp
|
R600/SI: Replace v1i32 type with i32 in imageload and sample intrinsics
|
2013-08-14 23:24:53 +00:00 |
