llvm-6502/lib/Target/Sparc
Evan Cheng c548428c5d Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an
extra operand to LOADX to specify the exact value extension type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30714 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-04 00:56:09 +00:00
..
.cvsignore ignore generated files 2005-09-07 23:47:44 +00:00
DelaySlotFiller.cpp Rename SPARC V8 target to be the LLVM SPARC target. 2006-02-05 05:50:24 +00:00
FPMover.cpp Move some methods out of MachineInstr into MachineOperand 2006-05-04 17:52:23 +00:00
Makefile Add the README files to the distribution. 2006-04-13 06:39:24 +00:00
README.txt Done 2006-02-09 20:00:19 +00:00
Sparc.h Patches to make the LLVM sources more -pedantic clean. Patch provided 2006-05-24 17:04:05 +00:00
Sparc.td getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd. 2006-05-18 00:12:58 +00:00
SparcAsmPrinter.cpp Adding dllimport, dllexport and external weak linkage types. 2006-09-14 18:23:27 +00:00
SparcInstrFormats.td Use a couple of multiclass patterns to factor some integer ops. 2006-09-01 22:28:02 +00:00
SparcInstrInfo.cpp Rename SPARC V8 target to be the LLVM SPARC target. 2006-02-05 05:50:24 +00:00
SparcInstrInfo.h Patches to make the LLVM sources more -pedantic clean. Patch provided 2006-05-24 17:04:05 +00:00
SparcInstrInfo.td Use a couple of multiclass patterns to factor some integer ops. 2006-09-01 22:28:02 +00:00
SparcISelDAGToDAG.cpp Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an 2006-10-04 00:56:09 +00:00
SparcRegisterInfo.cpp Completely eliminate def&use operands. Now a register operand is EITHER a 2006-09-05 02:31:13 +00:00
SparcRegisterInfo.h getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd. 2006-05-18 00:12:58 +00:00
SparcRegisterInfo.td Constify some methods. Patch provided by Anton Vayvod, thanks! 2006-08-17 22:00:08 +00:00
SparcSubtarget.cpp Patches to make the LLVM sources more -pedantic clean. Patch provided 2006-05-24 17:04:05 +00:00
SparcSubtarget.h Rename SPARC V8 target to be the LLVM SPARC target. 2006-02-05 05:50:24 +00:00
SparcTargetAsmInfo.cpp Break out target asm info into separate files. 2006-09-07 22:05:02 +00:00
SparcTargetAsmInfo.h Break out target asm info into separate files. 2006-09-07 22:05:02 +00:00
SparcTargetMachine.cpp 1. Remove condition on delete. 2006-09-07 23:39:26 +00:00
SparcTargetMachine.h 1. Remove condition on delete. 2006-09-07 23:39:26 +00:00

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9 
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling 
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for 
  leaf fns.
* Fill delay slots