Hao Liu 2825b8f0ea [AArch64]Implement the copy of two FPR8 registers by using FMOVss of two FPR32 registers in copyPhysReg. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201061 91177308-0d34-0410-b5e6-96231b3b80d8		2014-02-10 03:16:22 +00:00
..
128bit_load_store.ll
adc.ll
addsub_ext.ll
addsub-shifted.ll
addsub.ll
alloca.ll
analyze-branch.ll
assertion-rc-mismatch.ll
atomic-ops-not-barriers.ll
atomic-ops.ll
basic-pic.ll
bitfield-insert-0.ll
bitfield-insert.ll
bitfield.ll
blockaddress.ll
bool-loads.ll
breg.ll
callee-save.ll
code-model-large-abs.ll
compare-branch.ll
complex-copy-noneon.ll
concatvector-v8i8-bug.ll	[AArch64] Removed unused i8 type from FPR8 register class.	2014-01-24 22:36:53 +00:00
cond-sel.ll
directcond.ll
dp1.ll
dp2.ll
dp-3source.ll
extern-weak.ll
extract.ll
fastcc-reserved.ll
fastcc.ll
fcmp.ll
fcvt-fixed.ll
fcvt-int.ll
flags-multiuse.ll
floatdp_1source.ll
floatdp_2source.ll
fp128-folding.ll
fp128.ll
fp-cond-sel.ll
fp-dp3.ll
fpimm.ll
frameaddr.ll
func-argpassing.ll
func-calls.ll
global-alignment.ll
got-abuse.ll
i128-align.ll
illegal-float-ops.ll
init-array.ll
inline-asm-constraints-badI.ll
inline-asm-constraints-badK2.ll
inline-asm-constraints-badK.ll
inline-asm-constraints-badL.ll
inline-asm-constraints.ll
inline-asm-modifiers.ll
jump-table.ll
large-consts.ll
large-frame.ll
ldst-regoffset.ll
ldst-unscaledimm.ll
ldst-unsignedimm.ll
lit.local.cfg
literal_pools.ll
local_vars.ll
logical_shifted_reg.ll
logical-imm.ll
movw-consts.ll
movw-shift-encoding.ll
mul-lohi.ll	AArch64: don't try to handle [SU]MUL_LOHI nodes	2014-01-14 22:53:22 +00:00
neon-2velem-high.ll
neon-2velem.ll
neon-3vdiff.ll
neon-aba-abd.ll
neon-across.ll
neon-add-pairwise.ll
neon-add-sub.ll
neon-bitcast.ll
neon-bitwise-instructions.ll
neon-bsl.ll	[AArch64] Added vselect patterns with float and double types	2014-01-23 19:18:57 +00:00
neon-compare-instructions.ll
neon-copy.ll	[AArch64]Implement the copy of two FPR8 registers by using FMOVss of two FPR32 registers in copyPhysReg.	2014-02-10 03:16:22 +00:00
neon-copyPhysReg-tuple.ll
neon-crypto.ll	AArch64 & ARM: refactor crypto intrinsics to take scalars	2014-02-03 17:27:49 +00:00
neon-diagnostics.ll
neon-extract.ll	[AArch64 NEON] Fix a bug caused by undef lane when generating VEXT.	2014-01-21 01:48:52 +00:00
neon-facge-facgt.ll	ARM & AArch64: merge NEON absolute compare intrinsics	2014-02-04 14:55:42 +00:00
neon-fma.ll
neon-fpround_f128.ll	[AArch64 NEON] Add test case for vector FP_ROUND.	2014-01-26 02:23:33 +00:00
neon-frsqrt-frecp.ll
neon-halving-add-sub.ll
neon-load-store-v1i32.ll	[AArch64]Fix the problem can't select f16_to_f32 and f32_to_f16.	2014-01-17 06:23:30 +00:00
neon-max-min-pairwise.ll
neon-max-min.ll
neon-misc-scalar.ll
neon-misc.ll	[AArch64 NEON] Custom lower conversion between vector integer and vector floating point if element bit-width doesn't match.	2014-01-17 05:52:35 +00:00
neon-mla-mls.ll
neon-mov.ll
neon-mul-div.ll	[AArch64 NEON] Expand vector for UDIV/SDIV/UREM/SREM/FREM as neon doesn't support these operations.	2014-01-17 09:54:30 +00:00
neon-or-combine.ll
neon-perm.ll
neon-rounding-halving-add.ll
neon-rounding-shift.ll
neon-saturating-add-sub.ll
neon-saturating-rounding-shift.ll
neon-saturating-shift.ll
neon-scalar-abs.ll
neon-scalar-add-sub.ll
neon-scalar-by-elem-fma.ll
neon-scalar-by-elem-mul.ll
neon-scalar-compare.ll	ARM & AArch64: merge NEON absolute compare intrinsics	2014-02-04 14:55:42 +00:00
neon-scalar-copy.ll
neon-scalar-cvt.ll
neon-scalar-ext.ll	Improve pattern match from v1i8 to v1i32 for AArch64 Neon.	2014-01-26 04:55:53 +00:00
neon-scalar-extract-narrow.ll
neon-scalar-fabd.ll
neon-scalar-fcvt.ll
neon-scalar-fp-compare.ll
neon-scalar-mul.ll
neon-scalar-neg.ll
neon-scalar-recip.ll
neon-scalar-reduce-pairwise.ll
neon-scalar-rounding-shift.ll
neon-scalar-saturating-add-sub.ll
neon-scalar-saturating-rounding-shift.ll
neon-scalar-saturating-shift.ll
neon-scalar-shift-imm.ll
neon-scalar-shift.ll
neon-select_cc.ll	[AArch64 NEON] Lower SELECT_CC with vector operand.	2014-01-29 01:57:30 +00:00
neon-shift-left-long.ll
neon-shift.ll
neon-shl-ashr-lshr.ll
neon-simd-ldst-multi-elem.ll
neon-simd-ldst-one.ll
neon-simd-ldst.ll
neon-simd-post-ldst-multi-elem.ll
neon-simd-post-ldst-one.ll
neon-simd-shift.ll
neon-simd-tbl.ll
neon-simd-vget.ll
neon-truncStore-extLoad.ll
neon-vector-list-spill.ll
pic-eh-stubs.ll
regress-bitcast-formals.ll
regress-f128csel-flags.ll
regress-fp128-livein.ll
regress-tail-livereg.ll
regress-tblgen-chains.ll
regress-w29-reserved-with-fp.ll
regress-wzr-allocatable.ll
returnaddr.ll
setcc-takes-i32.ll
sext_inreg.ll	For AArch64, lowering sext_inreg and generate optimized code by using SXTL.	2014-01-15 05:08:01 +00:00
sibling-call.ll
sincos-expansion.ll
tail-call.ll
tls-dynamic-together.ll
tls-dynamics.ll
tls-execs.ll
tst-br.ll
variadic.ll
zero-reg.ll