llvm-6502/lib/CodeGen
2008-12-16 21:35:08 +00:00
..
AsmPrinter Do not print empty DW_AT_comp_dir. 2008-12-12 21:57:54 +00:00
SelectionDAG Preserve SourceValue information when lowering produces multiple loads from 2008-12-16 18:25:36 +00:00
BranchFolding.cpp Add a newline after this debug output. 2008-12-10 23:24:43 +00:00
CMakeLists.txt Experimental post-pass scheduling support. Post-pass scheduling 2008-11-19 23:18:57 +00:00
DeadMachineInstructionElim.cpp Rename AliasSet to SubRegs, to reflect changes in the surrounding code. 2008-10-16 01:06:18 +00:00
ELFWriter.cpp Fix MachineCodeEmitter to use uintptr_t instead of intptr_t. This avoids some overflow issues. Patch by Thomas Jablin. 2008-12-10 02:32:19 +00:00
ELFWriter.h Use raw_ostream throughout the AsmPrinter. 2008-08-21 00:14:44 +00:00
GCMetadata.cpp Tidy up several unbeseeming casts from pointer to intptr_t. 2008-09-04 17:05:41 +00:00
GCMetadataPrinter.cpp Use raw_ostream throughout the AsmPrinter. 2008-08-21 00:14:44 +00:00
GCStrategy.cpp Tidy up several unbeseeming casts from pointer to intptr_t. 2008-09-04 17:05:41 +00:00
IfConversion.cpp Fix typo. Patch by nlewycky. 2008-11-04 18:05:30 +00:00
IntrinsicLowering.cpp reapply Sanjiv's patch to genericize memcpy/memset/memmove to take an 2008-11-21 16:42:48 +00:00
LatencyPriorityQueue.cpp Add initial support for back-scheduling address computations, 2008-12-16 03:35:01 +00:00
LiveInterval.cpp Next round of earlyclobber handling. Approach the 2008-09-24 01:07:17 +00:00
LiveIntervalAnalysis.cpp Clarify some comments. 2008-12-08 04:53:23 +00:00
LiveStackAnalysis.cpp Livestacks really does preserve everything. 2008-09-22 22:26:15 +00:00
LiveVariables.cpp Silence unused variable warnings. 2008-11-21 20:00:59 +00:00
LLVMTargetMachine.cpp Run post-RA scheduling after branch folding, as it tends to 2008-11-24 17:22:52 +00:00
LoopAligner.cpp Avoid inserting noop's in the middle of a loop. 2008-11-27 01:16:00 +00:00
LowerSubregs.cpp Silence unused variable warnings. 2008-11-21 20:00:59 +00:00
MachineBasicBlock.cpp Switch the MachineOperand accessors back to the short names like 2008-10-03 15:45:36 +00:00
MachineDominators.cpp Change class' public PassInfo variables to by initialized with the 2008-05-13 02:05:11 +00:00
MachineFunction.cpp Make MachineFrameInfo::print not crash when no TargetFrameInfo is available. 2008-11-03 11:16:43 +00:00
MachineInstr.cpp Minor code simplification. 2008-12-09 22:45:08 +00:00
MachineLICM.cpp Switch the MachineOperand accessors back to the short names like 2008-10-03 15:45:36 +00:00
MachineLoopInfo.cpp Change class' public PassInfo variables to by initialized with the 2008-05-13 02:05:11 +00:00
MachineModuleInfo.cpp Fix a couple of Dwarf bugs. 2008-12-10 00:15:44 +00:00
MachinePassRegistry.cpp Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
MachineRegisterInfo.cpp Move createVirtualRegister out-of-line. 2008-12-08 04:54:11 +00:00
MachineSink.cpp Switch the MachineOperand accessors back to the short names like 2008-10-03 15:45:36 +00:00
MachOWriter.cpp Fix MachineCodeEmitter to use uintptr_t instead of intptr_t. This avoids some overflow issues. Patch by Thomas Jablin. 2008-12-10 02:32:19 +00:00
MachOWriter.h Use raw_ostream throughout the AsmPrinter. 2008-08-21 00:14:44 +00:00
Makefile Move all assembler printing related stuff into new libAsmPrinter 2008-08-17 13:53:04 +00:00
OcamlGC.cpp Rename some GC classes so that their roll will hopefully be clearer. 2008-08-17 18:44:35 +00:00
Passes.cpp Clean up the use of static and anonymous namespaces. This turned up 2008-05-13 00:00:25 +00:00
PBQP.cpp reorder #include order, patch by Kenneth Boyd! 2008-10-06 03:54:25 +00:00
PBQP.h Fix typos pointed out by Duncan. Also untabify these files. 2008-10-03 17:11:58 +00:00
PHIElimination.cpp Tidy up several unbeseeming casts from pointer to intptr_t. 2008-09-04 17:05:41 +00:00
PhysRegTracker.h Rename MRegisterInfo to TargetRegisterInfo. 2008-02-10 18:45:23 +00:00
PostRASchedulerList.cpp Eliminate the loop that walks the critical path. Instead, just track the 2008-12-16 19:27:52 +00:00
PreAllocSplitting.cpp Add code to renumber split intervals into new vregs. This is disabled for now until I finish working out some iterator invalidation issues. 2008-12-16 21:35:08 +00:00
PrologEpilogInserter.cpp Refactor code that adjusts the offsets of stack objects. 2008-11-07 01:48:58 +00:00
PseudoSourceValue.cpp Have PseudoSourceValue override Value::dump, so that it works 2008-12-03 21:37:21 +00:00
README.txt Remove tabs. 2008-08-22 00:04:26 +00:00
RegAllocBigBlock.cpp Minor fix debug for register allocation debug output. 2008-11-24 16:01:21 +00:00
RegAllocLinearScan.cpp - More pre-split fixes: spill slot live interval computation bug; restore point bug. 2008-10-29 08:39:34 +00:00
RegAllocLocal.cpp Drop the reg argument to isRegReDefinedByTwoAddr, which was redundant. 2008-12-05 05:45:42 +00:00
RegAllocPBQP.cpp Fix compilation error on MSVC. 2008-11-19 12:56:21 +00:00
RegAllocSimple.cpp Fix command-line option printing to print two spaces where needed, 2008-10-14 20:25:08 +00:00
RegisterCoalescer.cpp Clean up the use of static and anonymous namespaces. This turned up 2008-05-13 00:00:25 +00:00
RegisterScavenging.cpp Fix a typo in a comment. 2008-12-02 19:27:20 +00:00
ScheduleDAG.cpp Fix some register-alias-related bugs in the post-RA scheduler liveness 2008-12-16 03:25:46 +00:00
ScheduleDAGEmit.cpp Rewrite the SDep class, and simplify some of the related code. 2008-12-09 22:54:47 +00:00
ScheduleDAGInstrs.cpp Add initial support for back-scheduling address computations, 2008-12-16 03:35:01 +00:00
ScheduleDAGPrinter.cpp This getEdgeAttributes doesn't need a template argument. 2008-12-16 00:55:00 +00:00
ShadowStackGC.cpp Large mechanical patch. 2008-09-25 21:00:45 +00:00
SimpleRegisterCoalescing.cpp Remove val# defined by a remat'ed def that is now dead. 2008-10-27 23:21:01 +00:00
SimpleRegisterCoalescing.h Remove val# defined by a remat'ed def that is now dead. 2008-10-27 23:21:01 +00:00
StackProtector.cpp Rename stackprotector_create intrinsic to stackprotector. 2008-11-18 11:01:33 +00:00
StackSlotColoring.cpp Teach StackSlotColoring to update MachineMemOperands when 2008-12-05 05:31:14 +00:00
StrongPHIElimination.cpp Fix a bug in live-in detection that caused lost-copy problems to show up. 2008-10-12 20:39:30 +00:00
TargetInstrInfoImpl.cpp Split foldMemoryOperand into public non-virtual and protected virtual 2008-12-03 18:43:12 +00:00
TwoAddressInstructionPass.cpp Do the LiveVariables update before printing the instruction in 2008-11-12 17:15:19 +00:00
UnreachableBlockElim.cpp Invalidate debug/eh/gc labels when unreachable MBB is deleted. 2008-10-31 20:08:30 +00:00
VirtRegMap.cpp Fix PR3124: overly strict assert. 2008-12-02 02:15:36 +00:00
VirtRegMap.h Move #include to right place. 2008-06-04 09:16:33 +00:00

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelyhood the store may become dead.

//===---------------------------------------------------------------------===//

I think we should have a "hasSideEffects" flag (which is automatically set for
stuff that "isLoad" "isCall" etc), and the remat pass should eventually be able
to remat any instruction that has no side effects, if it can handle it and if
profitable.

For now, I'd suggest having the remat stuff work like this:

1. I need to spill/reload this thing.
2. Check to see if it has side effects.
3. Check to see if it is simple enough: e.g. it only has one register
destination and no register input.
4. If so, clone the instruction, do the xform, etc.

Advantages of this are:

1. the .td file describes the behavior of the instructions, not the way the
   algorithm should work.
2. as remat gets smarter in the future, we shouldn't have to be changing the .td
   files.
3. it is easier to explain what the flag means in the .td file, because you
   don't have to pull in the explanation of how the current remat algo works.

Some potential added complexities:

1. Some instructions have to be glued to it's predecessor or successor. All of
   the PC relative instructions and condition code setting instruction. We could
   mark them as hasSideEffects, but that's not quite right. PC relative loads
   from constantpools can be remat'ed, for example. But it requires more than
   just cloning the instruction. Some instructions can be remat'ed but it
   expands to more than one instruction. But allocator will have to make a
   decision.

4. As stated in 3, not as simple as cloning in some cases. The target will have
   to decide how to remat it. For example, an ARM 2-piece constant generation
   instruction is remat'ed as a load from constantpool.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvments:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4