Misha Brukman d36e30e623 * Changed Bcc instructions to behave like BPcc instructions ... * BPA and BPN do not take a %cc register as a parameter * SLL/SRL/SRA{r,i}5 are there for a reason - they are ONLY 32-bit instructions * Likewise, SLL/SRL/SRAX{r,i}6 are only 64-bit * Added WRCCR{r,i} opcodes git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6655 91177308-0d34-0410-b5e6-96231b3b80d8		2003-06-06 09:52:23 +00:00
..
Analysis	Be more robust in the face of undefined behavior.	2003-06-02 05:42:39 +00:00
Archive	Fixed 'prevalent'.	2003-04-23 02:59:05 +00:00
AsmParser	Fix bugs:	2003-05-21 17:48:56 +00:00
Bytecode	Fix bug: Assembler/2003-05-03-BytecodeReaderProblem.llx	2003-05-22 18:35:38 +00:00
CodeGen	Fix bug: Jello/2003-06-04-bzip2-bug.ll	2003-06-05 17:15:04 +00:00
ExecutionEngine	::: HACK ALERT ::: HACK ALERT ::: HACK ALERT ::: HACK ALERT ::: HACK ALERT :::	2003-06-06 06:59:55 +00:00
Linker	Fix Bug: Linker/2003-05-15-TypeProblem.ll	2003-05-15 16:30:55 +00:00
Support	Make _sure_ we don't go into an infinite loop if a signal happens!	2003-05-27 16:25:04 +00:00
Target	* Changed Bcc instructions to behave like BPcc instructions	2003-06-06 09:52:23 +00:00
Transforms	Fix bug: InstCombine/2003-06-05-BranchInvertInfLoop.ll	2003-06-05 20:12:51 +00:00
VMCore	Fix (bogus) possibly uninitialized warning	2003-06-05 21:01:26 +00:00
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