Bill Wendling de2b151dbf Consider this code snippet: ... float t1(int argc) { return (argc == 1123) ? 1.234f : 2.38213f; } We would generate truly awful code on ARM (those with a weak stomach should look away): _t1: movw r1, #1123 movs r2, #1 movs r3, #0 cmp r0, r1 mov.w r0, #0 it eq moveq r0, r2 movs r1, #4 cmp r0, #0 it ne movne r3, r1 adr r0, #LCPI1_0 ldr r0, [r0, r3] bx lr The problem was that legalization was creating a cascade of SELECT_CC nodes, for for the comparison of "argc == 1123" which was fed into a SELECT node for the ?: statement which was itself converted to a SELECT_CC node. This is because the ARM back-end doesn't have custom lowering for SELECT nodes, so it used the default "Expand". I added a fairly simple "LowerSELECT" to the ARM back-end. It takes care of this testcase, but can obviously be expanded to include more cases. Now we generate this, which looks optimal to me: _t1: movw r1, #1123 movs r2, #0 cmp r0, r1 adr r0, #LCPI0_0 it eq moveq r2, #4 ldr r0, [r0, r2] bx lr .align 2 LCPI0_0: .long 1075344593 @ float 2.382130e+00 .long 1067316150 @ float 1.234000e+00 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110799 91177308-0d34-0410-b5e6-96231b3b80d8		2010-08-11 08:43:16 +00:00
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Alpha
ARM	Consider this code snippet:	2010-08-11 08:43:16 +00:00
Blackfin
CBackend
CellSPU
CPP
Generic
MBlaze
Mips
MSP430
PIC16
PowerPC
SPARC
SystemZ
Thumb	Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.)	2010-08-11 06:51:54 +00:00
Thumb2	Report error if codegen tries to instantiate a ARM target when the cpu does support it. e.g. cortex-m* processors.	2010-08-11 07:17:46 +00:00
X86
XCore