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AsmParser
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InstPrinter
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[cleanup] Re-sort all the #include lines in LLVM using
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2015-01-14 11:23:27 +00:00 |
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MCTargetDesc
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Add r224985 back with fixes.
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2015-01-19 21:11:14 +00:00 |
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TargetInfo
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AMDGPU.h
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R600/SI: Use external symbols for scratch buffer
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2015-01-20 17:49:47 +00:00 |
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AMDGPU.td
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R600/SI: Add subtarget feature to enable VGPR spilling for all shader types
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2015-01-20 19:33:04 +00:00 |
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AMDGPUAlwaysInlinePass.cpp
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AMDGPUAsmPrinter.cpp
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R600/SI: Emit .hsa.version section for amdhsa OS
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2015-01-23 23:59:08 +00:00 |
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AMDGPUAsmPrinter.h
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std::unique_ptrify the MCStreamer argument to createAsmPrinter
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2015-01-18 20:29:04 +00:00 |
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AMDGPUCallingConv.td
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AMDGPUFrameLowering.cpp
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AMDGPUFrameLowering.h
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AMDGPUInstrInfo.cpp
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R600/SI: Don't shrink instructions whose e32 encoding doesn't exist
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2015-01-15 18:42:51 +00:00 |
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AMDGPUInstrInfo.h
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R600/SI: Don't shrink instructions whose e32 encoding doesn't exist
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2015-01-15 18:42:51 +00:00 |
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AMDGPUInstrInfo.td
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AMDGPUInstructions.td
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R600/SI: Add patterns for v_cvt_{flr|rpi}_i32_f32
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2015-01-15 23:58:35 +00:00 |
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AMDGPUIntrinsicInfo.cpp
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AMDGPUIntrinsicInfo.h
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AMDGPUIntrinsics.td
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AMDGPUISelDAGToDAG.cpp
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R600/SI: Move i64 -> v2i32 load promotion into AMDGPUDAGToDAGISel::Select()
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2015-01-23 22:05:45 +00:00 |
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AMDGPUISelLowering.cpp
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Move DataLayout back to the TargetMachine from TargetSubtargetInfo
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2015-01-26 19:03:15 +00:00 |
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AMDGPUISelLowering.h
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R600: Try to use lower types for 64bit division if possible
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2015-01-22 23:42:43 +00:00 |
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AMDGPUMachineFunction.cpp
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AMDGPUMachineFunction.h
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AMDGPUMCInstLower.cpp
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R600/SI: Use external symbols for scratch buffer
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2015-01-20 17:49:47 +00:00 |
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AMDGPUMCInstLower.h
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R600/SI: Don't shrink instructions whose e32 encoding doesn't exist
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2015-01-15 18:42:51 +00:00 |
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AMDGPUPromoteAlloca.cpp
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AMDGPURegisterInfo.cpp
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AMDGPURegisterInfo.h
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AMDGPURegisterInfo.td
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AMDGPUSubtarget.cpp
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R600/SI: Define a schedule model and enable the generic machine scheduler
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2015-01-29 16:55:25 +00:00 |
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AMDGPUSubtarget.h
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R600/SI: Define a schedule model and enable the generic machine scheduler
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2015-01-29 16:55:25 +00:00 |
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AMDGPUTargetMachine.cpp
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R600: Move DataLayout to AMDGPUTargetMachine
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2015-01-28 16:04:26 +00:00 |
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AMDGPUTargetMachine.h
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R600: Move DataLayout to AMDGPUTargetMachine
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2015-01-28 16:04:26 +00:00 |
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AMDGPUTargetTransformInfo.cpp
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AMDILCFGStructurizer.cpp
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AMDKernelCodeT.h
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CaymanInstructions.td
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CIInstructions.td
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CMakeLists.txt
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R600/SI: Spill VGPRs to scratch space for compute shaders
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2015-01-14 15:42:31 +00:00 |
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EvergreenInstructions.td
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R600/SI: Custom lower fround
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2015-01-21 18:18:25 +00:00 |
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LLVMBuild.txt
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Makefile
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Processors.td
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R600/SI: Define a schedule model
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2015-01-14 01:13:19 +00:00 |
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R600ClauseMergePass.cpp
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R600ControlFlowFinalizer.cpp
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R600Defines.h
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R600EmitClauseMarkers.cpp
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R600ExpandSpecialInstrs.cpp
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R600InstrFormats.td
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R600InstrInfo.cpp
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R600InstrInfo.h
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R600Instructions.td
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R600/SI: Custom lower fround
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2015-01-21 18:18:25 +00:00 |
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R600Intrinsics.td
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R600ISelLowering.cpp
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[SelectionDAG] Allow targets to specify legality of extloads' result
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2015-01-08 00:51:32 +00:00 |
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R600ISelLowering.h
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R600MachineFunctionInfo.cpp
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R600MachineFunctionInfo.h
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R600MachineScheduler.cpp
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R600MachineScheduler.h
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R600OptimizeVectorRegisters.cpp
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R600Packetizer.cpp
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R600RegisterInfo.cpp
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R600RegisterInfo.h
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R600RegisterInfo.td
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R600Schedule.td
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R600TextureIntrinsicsReplacer.cpp
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R700Instructions.td
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SIAnnotateControlFlow.cpp
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SIDefines.h
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R600/SI: Add subtarget feature to enable VGPR spilling for all shader types
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2015-01-20 19:33:04 +00:00 |
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SIFixSGPRCopies.cpp
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R600/SI: Remove VReg_32 register class
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2015-01-07 20:59:25 +00:00 |
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SIFixSGPRLiveRanges.cpp
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SIFoldOperands.cpp
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R600/SI: Add pattern for bitcasting fp immediates to integers
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2015-01-13 22:59:41 +00:00 |
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SIInsertWaits.cpp
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SIInstrFormats.td
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R600/SI: Add VI versions of LDS atomics
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2015-01-27 17:25:07 +00:00 |
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SIInstrInfo.cpp
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R600/SI: Add subtarget feature to enable VGPR spilling for all shader types
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2015-01-20 19:33:04 +00:00 |
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SIInstrInfo.h
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R600/SI: Don't shrink instructions whose e32 encoding doesn't exist
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2015-01-15 18:42:51 +00:00 |
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SIInstrInfo.td
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R600/SI: Don't set patterns for chip-specific instructions while having pseudos
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2015-01-27 17:25:11 +00:00 |
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SIInstructions.td
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R600/SI: Fix MIN3/MAX3 on VI, define MED3
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2015-01-27 17:25:15 +00:00 |
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SIIntrinsics.td
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SIISelLowering.cpp
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R600/SI: Add subtarget feature to enable VGPR spilling for all shader types
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2015-01-20 19:33:04 +00:00 |
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SIISelLowering.h
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R600/SI: Fix bad code with unaligned byte vector loads
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2015-01-14 01:35:22 +00:00 |
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SILoadStoreOptimizer.cpp
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SILowerControlFlow.cpp
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R600/SI: Add pattern for bitcasting fp immediates to integers
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2015-01-13 22:59:41 +00:00 |
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SILowerI1Copies.cpp
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R600/SI: Remove VReg_32 register class
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2015-01-07 20:59:25 +00:00 |
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SIMachineFunctionInfo.cpp
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R600/SI: Spill VGPRs to scratch space for compute shaders
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2015-01-14 15:42:31 +00:00 |
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SIMachineFunctionInfo.h
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R600/SI: Add subtarget feature to enable VGPR spilling for all shader types
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2015-01-20 19:33:04 +00:00 |
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SIPrepareScratchRegs.cpp
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R600/SI: Fix simple-loop.ll test
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2015-01-20 19:33:02 +00:00 |
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SIRegisterInfo.cpp
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R600/SI: Remove stray debug statements
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2015-01-29 16:55:28 +00:00 |
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SIRegisterInfo.h
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R600/SI: Define a schedule model and enable the generic machine scheduler
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2015-01-29 16:55:25 +00:00 |
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SIRegisterInfo.td
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R600/SI: Use RegisterOperands to specify which operands can accept immediates
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2015-01-12 19:33:18 +00:00 |
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SISchedule.td
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R600/SI: Define a schedule model
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2015-01-14 01:13:19 +00:00 |
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SIShrinkInstructions.cpp
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R600/SI: Don't shrink instructions whose e32 encoding doesn't exist
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2015-01-15 18:42:51 +00:00 |
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SITypeRewriter.cpp
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VIInstrFormats.td
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VIInstructions.td
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R600/SI: Add VI versions of MUBUF loads and stores
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2015-01-27 17:24:58 +00:00 |
