David Peixotto 1edc33b924 ARM integrated assembler generates incorrect nop opcode ... This patch fixes a bug in the assembler that was causing bad code to be emitted. When switching modes in an assembly file (e.g. arm to thumb mode) we would always emit the opcode from the original mode. Consider this small example: $ cat align.s .code 16 foo: add r0, r0 .align 3 add r0, r0 $ llvm-mc -triple armv7-none-linux align.s -filetype=obj -o t.o $ llvm-objdump -triple thumbv7 -d t.o Disassembly of section .text: foo: 0: 00 44 add r0, r0 2: 00 f0 20 e3 blx #4195904 6: 00 00 movs r0, r0 8: 00 44 add r0, r0 This shows that we have actually emitted an arm nop (e320f000) instead of a thumb nop. Unfortunately, this encodes to a thumb branch which causes bad things to happen when compiling assembly code with align directives. The fix is to notify the ARMAsmBackend when we switch mode. The MCMachOStreamer was already doing this correctly. This patch makes the same change for the MCElfStreamer. There is still a bug in the way nops are emitted for alignment because the MCAlignment fragment does not store the correct mode. The ARMAsmBackend will emit nops for the last mode it knew about. In the example above, we still generate an arm nop if we add a `.code 32` to the end of the file. PR18019 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195677 91177308-0d34-0410-b5e6-96231b3b80d8		2013-11-25 19:11:13 +00:00
..
AlignedBundling
2010-11-30-reloc-movt.s	Convert another llc -filetype=obj test.	2013-10-28 21:12:15 +00:00
2013-03-18-Br-to-label-named-like-reg.s
align_arm_2_thumb.s	ARM integrated assembler generates incorrect nop opcode	2013-11-25 19:11:13 +00:00
align_thumb_2_arm.s	ARM integrated assembler generates incorrect nop opcode	2013-11-25 19:11:13 +00:00
arm_addrmode2.s
arm_addrmode3.s
arm_fixups.s
arm_instructions.s
arm_word_directive.s
arm-aliases.s
arm-arithmetic-aliases.s
arm-it-block.s
arm-ldrd.s	[ARM] Use FileCheck instead of grep for ARM LDRD negative tests.	2013-09-30 17:31:26 +00:00
arm-memory-instructions.s	ARM: Teach assembler to enforce constraints for ARM LDRD destination register operands.	2013-09-27 13:28:17 +00:00
arm-shift-encoding.s
arm-thumb-cpus-default.s
arm-thumb-cpus.s
arm-thumb-trustzone.s
arm-trustzone.s
basic-arm-instructions-v8.s	Test cleanup for v8 instructions	2013-10-29 14:16:09 +00:00
basic-arm-instructions.s	[ARM] In ARMAsmParser, MatchCoprocessorOperandName() permitted p10 and p11 as operands for coprocessor instructions, resulting in encodings that clash with FP/NEON instruction encodings	2013-11-08 09:16:31 +00:00
basic-thumb2-instructions-v8.s	Test cleanup for v8 instructions	2013-10-29 14:16:09 +00:00
basic-thumb2-instructions.s	[ARM] In ARMAsmParser, MatchCoprocessorOperandName() permitted p10 and p11 as operands for coprocessor instructions, resulting in encodings that clash with FP/NEON instruction encodings	2013-11-08 09:16:31 +00:00
basic-thumb-instructions.s
bracket-darwin.s
bracket-exprs.s
crc32-thumb.s	ARM: Add subtarget feature for CRC	2013-10-29 09:47:35 +00:00
crc32.s	ARM: Add subtarget feature for CRC	2013-10-29 09:47:35 +00:00
cxx-global-constructor.ll
data-in-code.ll
deprecated-v8.s	[ARM] Warn on deprecated IT blocks in v8 AArch32 assembly.	2013-10-03 09:31:51 +00:00
diagnostics-noneon.s	ARM: mark various aliases with their architecture requirements.	2013-10-24 12:22:58 +00:00
diagnostics.s	ARM: diagnose invalid system LDM/STM	2013-11-12 21:32:41 +00:00
directive-cpu.s	[arm] Implement eabi_attribute, cpu, and fpu directives.	2013-10-28 17:51:12 +00:00
directive-eabi_attribute.s	[arm] Implement eabi_attribute, cpu, and fpu directives.	2013-10-28 17:51:12 +00:00
directive-fpu-multiple.s	[arm] Implement eabi_attribute, cpu, and fpu directives.	2013-10-28 17:51:12 +00:00
directive-fpu.s	[arm] Implement eabi_attribute, cpu, and fpu directives.	2013-10-28 17:51:12 +00:00
dot-req.s
eh-compact-pr0.s
eh-compact-pr1.s
eh-directive-cantunwind-diagnostics.s
eh-directive-cantunwind.s
eh-directive-fnend-diagnostics.s
eh-directive-fnstart-diagnostics.s
eh-directive-handlerdata.s
eh-directive-integrated-test.s
eh-directive-multiple-offsets.s
eh-directive-pad-diagnostics.s
eh-directive-pad.s
eh-directive-personality-diagnostics.s
eh-directive-personality.s
eh-directive-save-diagnoatics.s
eh-directive-save.s
eh-directive-section-comdat.s
eh-directive-section-multiple-func.s
eh-directive-section.s
eh-directive-setfp-diagnostics.s
eh-directive-setfp.s
eh-directive-text-section-multiple-func.s
eh-directive-text-section.s
eh-directive-vsave-diagnostics.s
eh-directive-vsave.s
elf-eflags-eabi.s
elf-jump24-fixup.s
elf-movt.s
elf-reloc-01.ll
elf-reloc-02.ll
elf-reloc-03.ll
elf-reloc-condcall.s
elf-thumbfunc-reloc.ll
elf-thumbfunc-reloc.s
elf-thumbfunc.s	ARM: allow .thumb_func to be separated from symbol definition	2013-10-25 12:49:50 +00:00
fp-armv8.s	[ARM] Add support for MVFR2 which is new in ARMv8	2013-11-11 19:56:13 +00:00
full_line_comment.s
hilo-16bit-relocations.s
idiv.s	Add hardware division as a default feature on Cortex-A15. Also add test cases to check this, and change diagnostics for the hwdiv-arm feature to something useful.	2013-10-18 10:18:40 +00:00
invalid-barrier.s	Test cleanup for v8 instructions	2013-10-29 14:16:09 +00:00
invalid-crc32.s
invalid-fp-armv8.s	Add subtarget feature support for Cortex-A53	2013-10-14 13:16:57 +00:00
invalid-hint-arm.s	Make ARM hint ranges consistent, and add tests for these ranges	2013-10-23 10:14:40 +00:00
invalid-hint-thumb.s	Make ARM hint ranges consistent, and add tests for these ranges	2013-10-23 10:14:40 +00:00
invalid-idiv.s	Add hardware division as a default feature on Cortex-A15. Also add test cases to check this, and change diagnostics for the hwdiv-arm feature to something useful.	2013-10-18 10:18:40 +00:00
invalid-neon-v8.s	Add subtarget feature support for Cortex-A53	2013-10-14 13:16:57 +00:00
lit.local.cfg
load-store-acquire-release-v8-thumb.s
load-store-acquire-release-v8.s
mapping-within-section.s
mode-switch.s
multi-section-mapping.s
neon-abs-encoding.s
neon-absdiff-encoding.s
neon-add-encoding.s
neon-bitcount-encoding.s
neon-bitwise-encoding.s
neon-cmp-encoding.s
neon-convert-encoding.s
neon-crypto.s	[ARMv8] Add support for the v8 cryptography extensions.	2013-09-19 11:59:01 +00:00
neon-dup-encoding.s
neon-minmax-encoding.s
neon-mov-encoding.s
neon-mul-accum-encoding.s
neon-mul-encoding.s
neon-neg-encoding.s
neon-pairwise-encoding.s
neon-reciprocal-encoding.s
neon-reverse-encoding.s
neon-satshift-encoding.s
neon-shift-encoding.s
neon-shiftaccum-encoding.s
neon-shuffle-encoding.s
neon-sub-encoding.s
neon-table-encoding.s
neon-v8.s
neon-vld-encoding.s
neon-vst-encoding.s
neon-vswp.s
neont2-abs-encoding.s
neont2-absdiff-encoding.s
neont2-add-encoding.s
neont2-bitcount-encoding.s
neont2-bitwise-encoding.s
neont2-cmp-encoding.s
neont2-convert-encoding.s
neont2-dup-encoding.s
neont2-minmax-encoding.s
neont2-mov-encoding.s
neont2-mul-accum-encoding.s
neont2-mul-encoding.s
neont2-neg-encoding.s
neont2-pairwise-encoding.s
neont2-reciprocal-encoding.s
neont2-reverse-encoding.s
neont2-satshift-encoding.s
neont2-shift-encoding.s
neont2-shiftaccum-encoding.s
neont2-shuffle-encoding.s
neont2-sub-encoding.s
neont2-table-encoding.s
neont2-vld-encoding.s
neont2-vst-encoding.s
obsolete-v8.s
pr11877.s
relocated-mapping.s
simple-fp-encoding.s
single-precision-fp.s	ARM: tweak test to pass on all platforms	2013-10-25 07:34:56 +00:00
thumb2-b.w-encodingT4.s
thumb2-branches.s
thumb2-diagnostics.s	[ARM] Fix Thumb(-2) diagnostic tests.	2013-09-30 18:50:51 +00:00
thumb2-ldrd.s	ARM: Teach assembler to enforce constraint for Thumb2 LDRD (literal/immediate) destination register operands.	2013-09-27 10:30:18 +00:00
thumb2-mclass.s
thumb2-narrow-dp.ll
thumb2-pldw.s
thumb-diagnostics.s	ARM: fix assert on unpredictable POP instruction.	2013-10-24 09:37:18 +00:00
thumb-fp-armv8.s
thumb-hints.s	ARM: permit bare dmb/dsb/isb aliases on Cortex-M0	2013-11-05 21:36:02 +00:00
thumb-invalid-crypto.txt	[ARMv8] Add support for the v8 cryptography extensions.	2013-09-19 11:59:01 +00:00
thumb-neon-crypto.s	[ARMv8] Add support for the v8 cryptography extensions.	2013-09-19 11:59:01 +00:00
thumb-neon-v8.s
thumb-only-conditionals.s	[ARM] In ARMAsmParser, MatchCoprocessorOperandName() permitted p10 and p11 as operands for coprocessor instructions, resulting in encodings that clash with FP/NEON instruction encodings	2013-11-08 09:16:31 +00:00
thumb-shift-encoding.s
thumb.s
v8_IT_manual.s	[ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (Thumb encodings)	2013-11-08 16:25:50 +00:00
vfp4.s	ARM: Mark double-precision instructions as such	2013-10-24 15:49:39 +00:00
vpush-vpop.s
xscale-attributes.ll	[ARM] Fix FP ABI attributes with no VFP enabled.	2013-10-11 16:03:43 +00:00