llvm-6502/lib/CodeGen
Cameron Zwarich e1497b9791 Refactor the LiveOutInfo interface into a few methods on FunctionLoweringInfo
and make the actual map private.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126376 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-24 10:00:08 +00:00
..
AsmPrinter Use DW_FORM_data2 for DW_AT_language and let users use DW_LANG_lo_user=0x8000 to DW_LANG_hi_user=0xffff range. 2011-02-23 22:37:04 +00:00
SelectionDAG Refactor the LiveOutInfo interface into a few methods on FunctionLoweringInfo 2011-02-24 10:00:08 +00:00
AggressiveAntiDepBreaker.cpp
AggressiveAntiDepBreaker.h
AllocationOrder.cpp
AllocationOrder.h
Analysis.cpp
AntiDepBreaker.h
BranchFolding.cpp Add more debugging output. 2011-02-21 23:39:48 +00:00
BranchFolding.h
CalcSpillWeights.cpp Move more fragments of spill weight calculation into CalcSpillWeights.h 2011-02-14 23:15:38 +00:00
CallingConvLower.cpp
CMakeLists.txt Move library stuff out of the toplevel CMakeLists.txt file. 2011-02-18 22:06:14 +00:00
CodeGen.cpp
CodePlacementOpt.cpp
CriticalAntiDepBreaker.cpp Fix PostRA antidependence breaker. 2011-02-08 17:39:46 +00:00
CriticalAntiDepBreaker.h Typo. 2011-02-09 22:55:48 +00:00
DeadMachineInstructionElim.cpp
DwarfEHPrepare.cpp
EdgeBundles.cpp
ELF.h
ELFCodeEmitter.cpp
ELFCodeEmitter.h
ELFWriter.cpp Move broken HasCommonSymbols to ELFWriter.cpp. 2011-02-14 16:51:08 +00:00
ELFWriter.h
ExpandISelPseudos.cpp
GCMetadata.cpp
GCMetadataPrinter.cpp
GCStrategy.cpp
IfConversion.cpp
InlineSpiller.cpp Use the same spill slot for all live ranges that descend form the same original 2011-02-24 01:07:55 +00:00
IntrinsicLowering.cpp
LatencyPriorityQueue.cpp
LiveDebugVariables.cpp DebugLoc associated with a machine instruction is used to emit location entries. DebugLoc associated with a DBG_VALUE is used to identify lexical scope of the variable. After register allocation, while inserting DBG_VALUE remember original debug location for the first instruction and reuse it, otherwise dwarf writer may be mislead in identifying the variable's scope. 2011-02-04 01:43:25 +00:00
LiveDebugVariables.h
LiveInterval.cpp Implement RAGreedy::splitAroundRegion and remove loop splitting. 2011-01-19 22:11:48 +00:00
LiveIntervalAnalysis.cpp Move more fragments of spill weight calculation into CalcSpillWeights.h 2011-02-14 23:15:38 +00:00
LiveIntervalUnion.cpp Add tags to live interval unions to avoid using stale queries. 2011-02-09 21:52:03 +00:00
LiveIntervalUnion.h Add tags to live interval unions to avoid using stale queries. 2011-02-09 21:52:03 +00:00
LiveRangeEdit.cpp This method belonged in VirtRegMap. 2011-02-19 00:38:43 +00:00
LiveRangeEdit.h This method belonged in VirtRegMap. 2011-02-19 00:38:43 +00:00
LiveStackAnalysis.cpp
LiveVariables.cpp
LLVMTargetMachine.cpp Add support for the --noexecstack option. 2011-01-23 17:55:27 +00:00
LocalStackSlotAllocation.cpp
LowerSubregs.cpp
MachineBasicBlock.cpp Add LiveIntervals::getLastSplitPoint(). 2011-02-04 19:33:11 +00:00
MachineCSE.cpp
MachineDominators.cpp
MachineFunction.cpp MachineConstantPoolValues are not uniqued, so they need to be freed if they 2011-02-22 08:54:30 +00:00
MachineFunctionAnalysis.cpp
MachineFunctionPass.cpp
MachineFunctionPrinterPass.cpp
MachineInstr.cpp
MachineLICM.cpp Sorry, several patches in one. 2011-01-20 08:34:58 +00:00
MachineLoopInfo.cpp
MachineLoopRanges.cpp
MachineModuleInfo.cpp
MachineModuleInfoImpls.cpp
MachinePassRegistry.cpp
MachineRegisterInfo.cpp Revert r124611 - "Keep track of incoming argument's location while emitting LiveIns." 2011-02-21 23:21:26 +00:00
MachineSink.cpp
MachineSSAUpdater.cpp
MachineVerifier.cpp Verify kill flags conservatively. 2011-02-04 00:39:18 +00:00
Makefile
ObjectCodeEmitter.cpp
OcamlGC.cpp
OptimizePHIs.cpp
Passes.cpp
PeepholeOptimizer.cpp Fix thinko. Cmp can be the first instruction in a MBB. 2011-02-15 05:00:24 +00:00
PHIElimination.cpp Adjust indenting of arguments. 2011-02-17 06:13:46 +00:00
PHIEliminationUtils.cpp
PHIEliminationUtils.h
PostRASchedulerList.cpp
PreAllocSplitting.cpp
ProcessImplicitDefs.cpp
PrologEpilogInserter.cpp
PrologEpilogInserter.h
PseudoSourceValue.cpp
README.txt
RegAllocBase.h Change the RAGreedy register assignment order so large live ranges are allocated first. 2011-02-22 23:01:52 +00:00
RegAllocBasic.cpp Change the RAGreedy register assignment order so large live ranges are allocated first. 2011-02-22 23:01:52 +00:00
RegAllocFast.cpp Mark that the return is using EAX so that we don't use it for some other 2011-02-04 22:44:08 +00:00
RegAllocGreedy.cpp Keep track of how many times a live range has been dequeued, and prioritize new ranges. 2011-02-23 00:56:56 +00:00
RegAllocLinearScan.cpp Avoid modifying the OneClassForEachPhysReg map while iterating over it. 2011-01-27 07:26:15 +00:00
RegAllocPBQP.cpp
RegisterCoalescer.cpp
RegisterScavenging.cpp
RenderMachineFunction.cpp
RenderMachineFunction.h
ScheduleDAG.cpp Introducing a new method of tracking register pressure. We can't 2011-02-04 03:18:17 +00:00
ScheduleDAGEmit.cpp
ScheduleDAGInstrs.cpp
ScheduleDAGInstrs.h
ScheduleDAGPrinter.cpp
ScoreboardHazardRecognizer.cpp Convert -enable-sched-cycles and -enable-sched-hazard to -disable 2011-01-21 05:51:33 +00:00
ShadowStackGC.cpp
ShrinkWrapping.cpp Fix bug found by new clang warning. 2011-01-20 02:43:19 +00:00
SimpleRegisterCoalescing.cpp Switch to SmallVector in SimpleRegisterCoalescing for a 3.5% speedup on 403.gcc. 2011-02-17 06:52:07 +00:00
SimpleRegisterCoalescing.h Add LiveIntervals::shrinkToUses(). 2011-02-08 00:03:05 +00:00
SjLjEHPrepare.cpp
SlotIndexes.cpp Tweak debug output from SlotIndexes. 2011-02-03 20:29:41 +00:00
Spiller.cpp
Spiller.h
SpillPlacement.cpp Trim debugging output. 2011-02-18 00:32:47 +00:00
SpillPlacement.h Add RAGreedy methods for splitting live ranges around regions. 2011-01-18 21:13:27 +00:00
SplitKit.cpp It is safe to ignore LastSplitPoint when the variable is not live out. 2011-02-23 18:26:31 +00:00
SplitKit.h Add SplitKit::isOriginalEndpoint and use it to force live range splitting to terminate. 2011-02-21 23:09:46 +00:00
Splitter.cpp
Splitter.h
StackProtector.cpp
StackSlotColoring.cpp
StrongPHIElimination.cpp Add some statistics to StrongPHIElimination. 2011-02-14 02:09:18 +00:00
TailDuplication.cpp Update comments. 2011-02-04 01:10:12 +00:00
TargetInstrInfoImpl.cpp Convert -enable-sched-cycles and -enable-sched-hazard to -disable 2011-01-21 05:51:33 +00:00
TargetLoweringObjectFileImpl.cpp Revert r125960, it's breaking darwin10 bootstrap. 2011-02-21 23:52:19 +00:00
TwoAddressInstructionPass.cpp After 3-addressifying a two-address instruction, update the register maps; add a missing check when considering whether it's profitable to commute. rdar://8977508. 2011-02-10 02:20:55 +00:00
UnreachableBlockElim.cpp
VirtRegMap.cpp Add VirtRegMap::rewrite() and use it in the new register allocators. 2011-02-18 22:03:18 +00:00
VirtRegMap.h This method belonged in VirtRegMap. 2011-02-19 00:38:43 +00:00
VirtRegRewriter.cpp VirtRegRewriter assertion fix. 2011-02-22 06:52:56 +00:00
VirtRegRewriter.h

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelyhood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvments:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.