llvm-6502/test/CodeGen/ARM
Rafael Espindola 0e5e3aacbe expand ISD::VACOPY
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31170 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-24 20:15:21 +00:00
..
argaddr.ll add a "load effective address" 2006-08-17 17:09:40 +00:00
bits.ll implement shl and sra 2006-09-08 17:36:23 +00:00
branch.ll add the SETULT condition code 2006-09-03 13:19:16 +00:00
call.ll add blx 2006-10-18 16:21:43 +00:00
constants.ll print common symbols 2006-10-19 13:30:40 +00:00
dg.exp
div.ll expand ISD::SDIV, ISD::UDIV, ISD::SREM and ISD::UREM 2006-10-17 21:05:33 +00:00
fp.ll cleanup some tests 2006-10-17 20:20:07 +00:00
fparith.ll add FABSS and FABSD 2006-10-17 20:33:13 +00:00
fpcmp.ll cleanup some tests 2006-10-17 20:20:07 +00:00
fpconv.ll cleanup some tests 2006-10-17 20:20:07 +00:00
fpmem.ll remove extra [] in stores 2006-10-17 18:29:14 +00:00
hello.ll use a 'register pressure reducing' scheduler 2006-08-04 12:48:42 +00:00
ldr.ll select code like 2006-08-14 19:01:24 +00:00
load.ll implement LDRB, LDRSB, LDRH and LDRSH 2006-10-16 17:17:22 +00:00
long.ll add the immediate to the Offset in eliminateFrameIndex 2006-10-17 14:34:02 +00:00
longarith.ll expand ISD::SHL_PARTS, ISD::SRA_PARTS and ISD::SRL_PARTS 2006-10-16 21:10:32 +00:00
mem.ll implement STRB and STRH 2006-10-23 20:34:27 +00:00
mul.ll Implement a MachineFunctionPass to fix the mul instruction 2006-09-19 15:49:25 +00:00
ret_arg1.ll
ret_arg2.ll
ret_arg3.ll
ret_arg4.ll
ret_arg5.ll initial implementation of ARMRegisterInfo::eliminateFrameIndex 2006-06-18 00:08:07 +00:00
ret_void.ll
select.ll more condition codes 2006-09-21 13:06:26 +00:00
vargs2.ll expand ISD::VACOPY 2006-10-24 20:15:21 +00:00
vargs.ll fix the spill code 2006-08-09 16:41:12 +00:00