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llvm-6502/test/CodeGen/ARM
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Bob Wilson eb0c3d3729 Replace NEON vabdl, vaba, and vabal intrinsics with combinations of the 
vabd intrinsic and add and/or zext operations.  In the case of vaba, this
also avoids the need for a DAG combine pattern to combine vabd with add.
Update tests.  Auto-upgrade the old intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112941 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 01:35:08 +00:00
..
2006-11-10-CycleInDAG.ll
…
2007-01-19-InfiniteLoop.ll
…
2007-03-07-CombinerCrash.ll
…
2007-03-13-InstrSched.ll
…
2007-03-21-JoinIntervalsCrash.ll
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2007-03-26-RegScavengerAssert.ll
Correct bogus module triple specifications.
2010-08-30 10:48:29 +00:00
2007-03-27-RegScavengerAssert.ll
…
2007-03-30-RegScavengerAssert.ll
…
2007-04-02-RegScavengerAssert.ll
…
2007-04-03-PEIBug.ll
…
2007-04-03-UndefinedSymbol.ll
…
2007-04-30-CombinerCrash.ll
…
2007-05-03-BadPostIndexedLd.ll
…
2007-05-07-jumptoentry.ll
…
2007-05-07-tailmerge-1.ll
Remove the -enable-sjlj-eh option, which doesn't do anything.
2010-05-02 15:36:26 +00:00
2007-05-09-tailmerge-2.ll
Remove the -enable-sjlj-eh option, which doesn't do anything.
2010-05-02 15:36:26 +00:00
2007-05-14-InlineAsmCstCrash.ll
…
2007-05-14-RegScavengerAssert.ll
…
2007-05-22-tailmerge-3.ll
Remove the -enable-sjlj-eh option, which doesn't do anything.
2010-05-02 15:36:26 +00:00
2007-05-23-BadPreIndexedStore.ll
…
2007-05-31-RegScavengerInfiniteLoop.ll
Correct bogus module triple specifications.
2010-08-30 10:48:29 +00:00
2007-08-15-ReuseBug.ll
…
2008-02-04-LocalRegAllocBug.ll
Remove the local register allocator.
2010-06-15 21:58:33 +00:00
2008-02-29-RegAllocLocal.ll
Remove the local register allocator.
2010-06-15 21:58:33 +00:00
2008-03-05-SxtInRegBug.ll
…
2008-03-07-RegScavengerAssert.ll
…
2008-04-04-ScavengerAssert.ll
…
2008-04-10-ScavengerAssert.ll
…
2008-04-11-PHIofImpDef.ll
…
2008-05-19-LiveIntervalsBug.ll
…
2008-05-19-ScavengerAssert.ll
…
2008-07-17-Fdiv.ll
…
2008-07-24-CodeGenPrepCrash.ll
…
2008-08-07-AsmPrintBug.ll
…
2008-09-14-CoalescerBug.ll
…
2008-09-17-CoalescerBug.ll
…
2008-11-18-ScavengerAssert.ll
…
2009-02-16-SpillerBug.ll
…
2009-02-22-SoftenFloatVaArg.ll
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2009-02-27-SpillerBug.ll
…
2009-03-07-SpillerBug.ll
…
2009-03-09-AddrModeBug.ll
…
2009-04-06-AsmModifier.ll
…
2009-04-08-AggregateAddr.ll
…
2009-04-08-FloatUndef.ll
…
2009-04-08-FREM.ll
…
2009-04-09-RegScavengerAsm.ll
…
2009-05-05-DAGCombineBug.ll
Correct some bogus target triples.
2010-05-07 17:03:48 +00:00
2009-05-07-RegAllocLocal.ll
Remove the local register allocator.
2010-06-15 21:58:33 +00:00
2009-05-11-CodePlacementCrash.ll
…
2009-05-18-InlineAsmMem.ll
…
2009-06-02-ISelCrash.ll
…
2009-06-04-MissingLiveIn.ll
…
2009-06-12-RegScavengerAssert.ll
…
2009-06-15-RegScavengerAssert.ll
…
2009-06-19-RegScavengerAssert.ll
…
2009-06-22-CoalescerBug.ll
Remove arm_apcscc from the test files. It is the default and doing this
2010-06-17 15:18:27 +00:00
2009-06-30-RegScavengerAssert2.ll
Remove arm_apcscc from the test files. It is the default and doing this
2010-06-17 15:18:27 +00:00
2009-06-30-RegScavengerAssert3.ll
Remove arm_apcscc from the test files. It is the default and doing this
2010-06-17 15:18:27 +00:00
2009-06-30-RegScavengerAssert4.ll
Remove arm_apcscc from the test files. It is the default and doing this
2010-06-17 15:18:27 +00:00
2009-06-30-RegScavengerAssert5.ll
Remove arm_apcscc from the test files. It is the default and doing this
2010-06-17 15:18:27 +00:00
2009-06-30-RegScavengerAssert.ll
Remove arm_apcscc from the test files. It is the default and doing this
2010-06-17 15:18:27 +00:00
2009-07-01-CommuteBug.ll
Remove arm_apcscc from the test files. It is the default and doing this
2010-06-17 15:18:27 +00:00
2009-07-09-asm-p-constraint.ll
…
2009-07-18-RewriterBug.ll
Remove arm_apcscc from the test files. It is the default and doing this
2010-06-17 15:18:27 +00:00
2009-07-22-ScavengerAssert.ll
Remove arm_apcscc from the test files. It is the default and doing this
2010-06-17 15:18:27 +00:00
2009-07-22-SchedulerAssert.ll
Remove arm_apcscc from the test files. It is the default and doing this
2010-06-17 15:18:27 +00:00
2009-07-29-VFP3Registers.ll
Remove arm_apcscc from the test files. It is the default and doing this
2010-06-17 15:18:27 +00:00
2009-08-02-RegScavengerAssert-Neon.ll
Remove arm_apcscc from the test files. It is the default and doing this
2010-06-17 15:18:27 +00:00
2009-08-04-RegScavengerAssert-2.ll
Set the mtriple in some tests so that they use AAPCS.
2010-06-15 20:42:00 +00:00
2009-08-04-RegScavengerAssert.ll
Set the mtriple in some tests so that they use AAPCS.
2010-06-15 20:42:00 +00:00
2009-08-15-RegScavenger-EarlyClobber.ll
Set the mtriple in some tests so that they use AAPCS.
2010-06-15 20:42:00 +00:00
2009-08-15-RegScavengerAssert.ll
Set the mtriple in some tests so that they use AAPCS.
2010-06-15 20:42:00 +00:00
2009-08-21-PostRAKill2.ll
Remove arm_apcscc from the test files. It is the default and doing this
2010-06-17 15:18:27 +00:00
2009-08-21-PostRAKill3.ll
Remove arm_apcscc from the test files. It is the default and doing this
2010-06-17 15:18:27 +00:00
2009-08-21-PostRAKill4.ll
Remove arm_apcscc from the test files. It is the default and doing this
2010-06-17 15:18:27 +00:00
2009-08-21-PostRAKill.ll
Remove arm_apcscc from the test files. It is the default and doing this
2010-06-17 15:18:27 +00:00
2009-08-23-linkerprivate.ll
Implement the "linker_private_weak" linkage type. This will be used for
2010-07-01 21:55:59 +00:00
2009-08-26-ScalarToVector.ll
Remove arm_apcscc from the test files. It is the default and doing this
2010-06-17 15:18:27 +00:00
2009-08-27-ScalarToVector.ll
Remove arm_apcscc from the test files. It is the default and doing this
2010-06-17 15:18:27 +00:00
2009-08-29-ExtractEltf32.ll
Remove arm_apcscc from the test files. It is the default and doing this
2010-06-17 15:18:27 +00:00
2009-08-29-TooLongSplat.ll
Remove arm_apcscc from the test files. It is the default and doing this
2010-06-17 15:18:27 +00:00
2009-08-31-LSDA-Name.ll
Remove arm_apcscc from the test files. It is the default and doing this
2010-06-17 15:18:27 +00:00
2009-08-31-TwoRegShuffle.ll
…
2009-09-01-PostRAProlog.ll
Remove arm_apcscc from the test files. It is the default and doing this
2010-06-17 15:18:27 +00:00
2009-09-09-AllOnes.ll
Remove arm_apcscc from the test files. It is the default and doing this
2010-06-17 15:18:27 +00:00
2009-09-09-fpcmp-ole.ll
…
2009-09-10-postdec.ll
…
2009-09-13-InvalidSubreg.ll
…
2009-09-13-InvalidSuperReg.ll
…
2009-09-20-LiveIntervalsBug.ll
…
2009-09-21-LiveVariablesBug.ll
…
2009-09-22-LiveVariablesBug.ll
…
2009-09-23-LiveVariablesBug.ll
…
2009-09-24-spill-align.ll
Remove arm_apcscc from the test files. It is the default and doing this
2010-06-17 15:18:27 +00:00
2009-09-27-CoalescerBug.ll
…
2009-09-28-LdStOptiBug.ll
Remove the arm_aapcscc marker from the tests. It is the default
2010-06-15 19:04:29 +00:00
2009-10-02-NEONSubregsBug.ll
…
2009-10-21-InvalidFNeg.ll
…
2009-10-27-double-align.ll
Remove the arm_aapcscc marker from the tests. It is the default
2010-06-15 19:04:29 +00:00
2009-10-30.ll
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2009-11-01-NeonMoves.ll
Generalize the pre-coalescing of extract_subregs feeding reg_sequences,
2010-06-15 05:56:31 +00:00
2009-11-02-NegativeLane.ll
Change CodeGen/ARM/2009-11-02-NegativeLane.ll to use 16-bit vector elements
2010-05-21 21:05:32 +00:00
2009-11-07-SubRegAsmPrinting.ll
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2009-11-13-CoalescerCrash.ll
…
2009-11-13-ScavengerAssert2.ll
…
2009-11-13-ScavengerAssert.ll
…
2009-11-13-VRRewriterCrash.ll
…
2009-11-30-LiveVariablesBug.ll
…
2009-12-02-vtrn-undef.ll
Add a testcase for svn 111208.
2010-08-16 23:44:29 +00:00
2010-03-04-eabi-fp-spill.ll
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2010-03-04-stm-undef-addr.ll
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2010-03-18-ldm-rtrn.ll
…
2010-04-07-DbgValueOtherTargets.ll
…
2010-04-09-NeonSelect.ll
Remove arm_apcscc from the test files. It is the default and doing this
2010-06-17 15:18:27 +00:00
2010-04-13-v2f64SplitArg.ll
Remove arm_apcscc from the test files. It is the default and doing this
2010-06-17 15:18:27 +00:00
2010-04-14-SplitVector.ll
Remove arm_apcscc from the test files. It is the default and doing this
2010-06-17 15:18:27 +00:00
2010-04-15-ScavengerDebugValue.ll
Remove arm_apcscc from the test files. It is the default and doing this
2010-06-17 15:18:27 +00:00
2010-05-14-IllegalType.ll
Allow TargetLowering::getRegClassFor() to be called on illegal types. Also
2010-05-15 02:18:07 +00:00
2010-05-17-DAGCombineAssert.ll
FIX PR7158. SimplifyVBinOp was asserting when it fails to constant fold (op (build_vector), (build_vector)).
2010-05-18 00:03:40 +00:00
2010-05-17-FastAllocCrash.ll
Avoid allocating the same physreg to multiple virtregs in one instruction.
2010-05-17 17:18:59 +00:00
2010-05-18-LocalAllocCrash.ll
Remove arm_apcscc from the test files. It is the default and doing this
2010-06-17 15:18:27 +00:00
2010-05-18-PostIndexBug.ll
Remove arm_apcscc from the test files. It is the default and doing this
2010-06-17 15:18:27 +00:00
2010-05-19-Shuffles.ll
Handle Neon v2f64 and v2i64 vector shuffles as register copies.
2010-05-20 18:39:53 +00:00
2010-05-20-NEONSpillCrash.ll
Add alignment arguments to all the NEON load/store intrinsics.
2010-08-27 17:13:24 +00:00
2010-05-21-BuildVector.ll
Add alignment arguments to all the NEON load/store intrinsics.
2010-08-27 17:13:24 +00:00
2010-06-11-vmovdrr-bitcast.ll
Add alignment arguments to all the NEON load/store intrinsics.
2010-08-27 17:13:24 +00:00
2010-06-21-LdStMultipleBug.ll
Fix PR7421: bug in kill transferring logic. It was ignoring loads / stores which have already been processed.
2010-06-21 21:21:14 +00:00
2010-06-21-nondarwin-tc.ll
Temporarily disable tail calls on ARM to work around some linker problems.
2010-08-13 22:43:33 +00:00
2010-06-25-Thumb2ITInvalidIterator.ll
Thumb2ITBlockPass: Fix a possible dereference of an invalid iterator. This was
2010-06-25 23:14:54 +00:00
2010-06-28-DAGCombineUndef.ll
Unlike other targets, ARM now uses BUILD_VECTORs post-legalization so they
2010-06-28 23:40:25 +00:00
2010-06-29-PartialRedefFastAlloc.ll
Add alignment arguments to all the NEON load/store intrinsics.
2010-08-27 17:13:24 +00:00
2010-06-29-SubregImpDefs.ll
Fix a register scavenger crash when dealing with undefined subregs.
2010-06-29 18:42:49 +00:00
2010-07-26-GlobalMerge.ll
Currently EH lowering code expects typeinfo to be global only.
2010-07-26 18:45:39 +00:00
2010-08-04-EHCrash.ll
Testcase for r110248.
2010-08-04 21:56:30 +00:00
addrmode.ll
…
aliases.ll
…
align.ll
…
alloca.ll
In the presence of variable sized objects, allocate an emergency spill slot.
2010-07-09 20:27:06 +00:00
argaddr.ll
…
arguments2.ll
…
arguments3.ll
…
arguments4.ll
…
arguments5.ll
…
arguments6.ll
…
arguments7.ll
Fix declarations in a few more tests.
2010-04-17 21:29:25 +00:00
arguments8.ll
Fix declarations in a few more tests.
2010-04-17 21:29:25 +00:00
arguments_f64_backfill.ll
…
arguments-nosplit-double.ll
…
arguments-nosplit-i64.ll
…
arguments.ll
Fix eabi calling convention when a 64 bit value shadows r3.
2010-08-06 15:35:32 +00:00
arm-asm.ll
…
arm-frameaddr.ll
Remove the arm_aapcscc marker from the tests. It is the default
2010-06-15 19:04:29 +00:00
arm-negative-stride.ll
…
arm-returnaddr.ll
Thumb1 functions using @llvm.returnaddress were not saving the incoming LR.
2010-06-22 22:04:24 +00:00
armv4.ll
Remove the arm_aapcscc marker from the tests. It is the default
2010-06-15 19:04:29 +00:00
bfc.ll
…
bfi.ll
Add combiner patterns to more effectively utilize the BFI (bitfield insert)
2010-07-17 03:30:54 +00:00
bfx.ll
Update ARM DAGtoDAG for matching UBFX instruction for unsigned bitfield
2010-04-22 23:24:18 +00:00
bic.ll
…
bits.ll
…
bx_fold.ll
…
call_nolink.ll
…
call-tc.ll
Temporarily disable tail calls on ARM to work around some linker problems.
2010-08-13 22:43:33 +00:00
call.ll
Remove a tail call, and move some CHECKs to the
2010-06-04 01:01:04 +00:00
carry.ll
…
clz.ll
…
code-placement.ll
PHI elimination should not break back edge. It can cause some significant code placement issues. rdar://8263994
2010-08-17 01:20:36 +00:00
compare-call.ll
…
constants.ll
…
crash-O0.ll
When using ADDri to get the address of a stack object, 255 is a conservative
2010-06-18 20:59:25 +00:00
cse-libcalls.ll
…
ctors_dtors.ll
…
ctz.ll
…
dg.exp
…
div.ll
Report error if codegen tries to instantiate a ARM target when the cpu does support it. e.g. cortex-m* processors.
2010-08-11 07:17:46 +00:00
dyn-stackalloc.ll
…
extloadi1.ll
…
fabss.ll
Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
2010-05-21 00:43:17 +00:00
fadds.ll
Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
2010-05-21 00:43:17 +00:00
fast-isel.ll
Add another basic test cribbed from the x86 fast-isel tests.
2010-08-25 07:57:29 +00:00
fcopysign.ll
…
fdivs.ll
Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
2010-05-21 00:43:17 +00:00
fixunsdfdi.ll
…
flag-crash.ll
It's possible that a flag is added to the SDNode that points back to the
2010-06-24 22:00:37 +00:00
fmacs.ll
Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
2010-05-21 00:43:17 +00:00
fmdrr-fmrrd.ll
…
fmscs.ll
Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
2010-05-21 00:43:17 +00:00
fmuls.ll
Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
2010-05-21 00:43:17 +00:00
fnegs.ll
…
fnmacs.ll
…
fnmscs.ll
Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
2010-05-21 00:43:17 +00:00
fnmul.ll
…
fnmuls.ll
Fix an unnecessary XFAIL
2010-09-02 20:19:24 +00:00
formal.ll
…
fp16.ll
…
fp_convert.ll
…
fp.ll
…
fparith.ll
…
fpcmp_ueq.ll
…
fpcmp-opt.ll
Split -enable-finite-only-fp-math to two options:
2010-07-15 22:07:12 +00:00
fpcmp.ll
…
fpconsts.ll
Remove arm_apcscc from the test files. It is the default and doing this
2010-06-17 15:18:27 +00:00
fpconv.ll
…
fpmem.ll
…
fpow.ll
…
fpowi.ll
Correct bogus module triple specifications.
2010-08-30 10:48:29 +00:00
fptoint.ll
…
fsubs.ll
…
globals.ll
Start function numbering at 0.
2010-04-17 16:29:15 +00:00
hardfloat_neon.ll
…
hello.ll
…
hidden-vis-2.ll
…
hidden-vis-3.ll
Start function numbering at 0.
2010-04-17 16:29:15 +00:00
hidden-vis.ll
…
iabs.ll
…
ifcvt1.ll
…
ifcvt2.ll
Allow ARM if-converter to be run after post allocation scheduling.
2010-06-18 23:09:54 +00:00
ifcvt3.ll
…
ifcvt4.ll
…
ifcvt5.ll
Fix a bug which prevented tail merging of return instructions in
2010-05-03 14:35:47 +00:00
ifcvt6.ll
Reinstate correct test, remove the real invalidated test.
2010-06-23 18:56:06 +00:00
ifcvt7.ll
…
ifcvt8.ll
…
ifcvt9.ll
…
illegal-vector-bitcast.ll
…
imm.ll
…
indirectbr.ll
Remove arm_apcscc from the test files. It is the default and doing this
2010-06-17 15:18:27 +00:00
inlineasm2.ll
…
inlineasm3.ll
Remove arm_apcscc from the test files. It is the default and doing this
2010-06-17 15:18:27 +00:00
inlineasm-imm-arm.ll
…
inlineasm.ll
llvm can't correctly support 'H', 'Q' and 'R' modifiers. Just mark it an error.
2010-05-27 22:08:38 +00:00
insn-sched1.ll
Remove more tail calls.
2010-06-04 01:01:24 +00:00
ispositive.ll
…
large-stack.ll
…
ldm.ll
Remove more tail calls.
2010-06-04 01:01:24 +00:00
ldr_ext.ll
…
ldr_frame.ll
…
ldr_post.ll
…
ldr_pre.ll
…
ldr.ll
…
ldrd.ll
…
load.ll
…
long_shift.ll
Update test to match output of optimize compares for ARM.
2010-08-11 01:05:02 +00:00
long-setcc.ll
…
long.ll
…
lsr-code-insertion.ll
Change if-conversion block size limit checks to add some flexibility.
2010-06-25 22:42:03 +00:00
lsr-on-unrolled-loops.ll
Now that register allocation properly considers reserved regs, simplify the
2010-09-02 18:14:29 +00:00
lsr-scale-addr-mode.ll
…
machine-cse-cmp.ll
Re-apply 105308 with fix.
2010-06-04 23:28:13 +00:00
mem.ll
…
memcpy-inline.ll
…
memfunc.ll
…
mls.ll
…
movt-movw-global.ll
…
movt.ll
…
mul_const.ll
Some cheap DAG combine goodness for multiplication with a particular constant.
2010-05-15 18:16:59 +00:00
mul.ll
…
mulhi.ll
…
mvn.ll
…
neon_arith1.ll
…
neon_ld1.ll
…
neon_ld2.ll
…
neon_minmax.ll
…
pack.ll
Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoid
2010-08-17 17:23:19 +00:00
pr3502.ll
…
private.ll
…
reg_sequence.ll
Convert VLD1 and VLD2 instructions to use pseudo-instructions until
2010-09-02 16:00:54 +00:00
remat.ll
When sending stats output to stdout for grepping, don't emit normal
2010-08-18 22:22:44 +00:00
ret0.ll
…
ret_arg1.ll
…
ret_arg2.ll
…
ret_arg3.ll
…
ret_arg4.ll
…
ret_arg5.ll
…
ret_f32_arg2.ll
…
ret_f32_arg5.ll
…
ret_f64_arg2.ll
…
ret_f64_arg_reg_split.ll
…
ret_f64_arg_split.ll
…
ret_f64_arg_stack.ll
…
ret_i64_arg2.ll
…
ret_i64_arg3.ll
…
ret_i64_arg_split.ll
…
ret_i128_arg2.ll
…
ret_void.ll
…
rev.ll
…
sbfx.ll
add a simple dag combine to replace trivial shl+lshr with
2010-04-15 05:28:43 +00:00
section.ll
…
select_xform.ll
…
select-imm.ll
Remove arm_apcscc from the test files. It is the default and doing this
2010-06-17 15:18:27 +00:00
select.ll
Consider this code snippet:
2010-08-11 08:43:16 +00:00
shifter_operand.ll
…
smul.ll
…
spill-q.ll
Add alignment arguments to all the NEON load/store intrinsics.
2010-08-27 17:13:24 +00:00
stack-frame.ll
…
stm.ll
…
str_post.ll
…
str_pre-2.ll
…
str_pre.ll
…
str_trunc.ll
…
sub.ll
Improve 64-subtraction of immediates when parts of the immediate can fit
2010-07-14 17:45:16 +00:00
sxt_rot.ll
…
t2-imm.ll
Fix borken test
2010-08-30 23:41:49 +00:00
tail-opts.ll
…
thread_pointer.ll
…
tls1.ll
…
tls2.ll
…
tls3.ll
…
trap.ll
Remove arm_apcscc from the test files. It is the default and doing this
2010-06-17 15:18:27 +00:00
trunc_ldr.ll
…
truncstore-dag-combine.ll
…
tst_teq.ll
…
uint64tof64.ll
…
unaligned_load_store.ll
Remove arm_apcscc from the test files. It is the default and doing this
2010-06-17 15:18:27 +00:00
unord.ll
…
uxt_rot.ll
…
uxtb.ll
…
va_arg.ll
Fix va_arg for doubles. With this patch VAARG nodes always contain the
2010-07-11 04:01:49 +00:00
vaba.ll
Replace NEON vabdl, vaba, and vabal intrinsics with combinations of the
2010-09-03 01:35:08 +00:00
vabd.ll
Replace NEON vabdl, vaba, and vabal intrinsics with combinations of the
2010-09-03 01:35:08 +00:00
vabs.ll
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vadd.ll
Remove NEON vaddl, vaddw, vsubl, and vsubw intrinsics. Instead, use llvm
2010-08-29 05:57:34 +00:00
vargs_align.ll
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vargs.ll
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vbits.ll
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vbsl.ll
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vceq.ll
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vcge.ll
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vcgt.ll
Intrinsics which do a vector compare (results are all zero or all ones) are modeled as icmp / fcmp + sext. This is turned into a vsetcc by dag combine (yes, not a good long term solution). The targets can then isel the vsetcc to the appropriate instruction.
2010-05-19 01:08:17 +00:00
vcnt.ll
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vcombine.ll
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vcvt.ll
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vdup.ll
Add an ARM-specific DAG combining to avoid redundant VDUPLANE nodes.
2010-07-14 01:22:12 +00:00
vext.ll
Allow more cases of undef shuffle indices and add tests for them.
2010-08-17 05:54:34 +00:00
vfcmp.ll
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vfp.ll
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vget_lane.ll
Don't create neon moves in CopyRegToReg. NEONMoveFixPass will do the conversion
2010-07-06 16:24:34 +00:00
vhadd.ll
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vhsub.ll
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vicmp.ll
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vld1.ll
Add alignment arguments to all the NEON load/store intrinsics.
2010-08-27 17:13:24 +00:00
vld2.ll
Add alignment arguments to all the NEON load/store intrinsics.
2010-08-27 17:13:24 +00:00
vld3.ll
Add alignment arguments to all the NEON load/store intrinsics.
2010-08-27 17:13:24 +00:00
vld4.ll
Add alignment arguments to all the NEON load/store intrinsics.
2010-08-27 17:13:24 +00:00
vldlane.ll
Add alignment arguments to all the NEON load/store intrinsics.
2010-08-27 17:13:24 +00:00
vminmax.ll
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vmla.ll
Remove NEON vmull, vmlal, and vmlsl intrinsics, replacing them with multiply,
2010-09-01 23:50:19 +00:00
vmls.ll
Remove NEON vmull, vmlal, and vmlsl intrinsics, replacing them with multiply,
2010-09-01 23:50:19 +00:00
vmov.ll
Remove NEON vmovn intrinsic, replacing it with vector truncate operations.
2010-08-30 20:02:30 +00:00
vmul.ll
Remove NEON vmull, vmlal, and vmlsl intrinsics, replacing them with multiply,
2010-09-01 23:50:19 +00:00
vneg.ll
Fix tests to use fadd, fsub, and fmul, instead of add, sub, and mul,
2010-05-03 22:36:46 +00:00
vpadal.ll
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vpadd.ll
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vpminmax.ll
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vqadd.ll
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vqdmul.ll
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vqshl.ll
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vqshrn.ll
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vqsub.ll
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vrec.ll
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vrev.ll
Allow more cases of undef shuffle indices and add tests for them.
2010-08-17 05:54:34 +00:00
vshift.ll
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vshiftins.ll
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vshl.ll
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vshll.ll
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vshrn.ll
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vsra.ll
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vst1.ll
Add alignment arguments to all the NEON load/store intrinsics.
2010-08-27 17:13:24 +00:00
vst2.ll
Add alignment arguments to all the NEON load/store intrinsics.
2010-08-27 17:13:24 +00:00
vst3.ll
Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just like
2010-08-27 23:18:17 +00:00
vst4.ll
Add alignment arguments to all the NEON load/store intrinsics.
2010-08-27 17:13:24 +00:00
vstlane.ll
Add alignment arguments to all the NEON load/store intrinsics.
2010-08-27 17:13:24 +00:00
vsub.ll
Remove NEON vaddl, vaddw, vsubl, and vsubw intrinsics. Instead, use llvm
2010-08-29 05:57:34 +00:00
vtbl.ll
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vtrn.ll
Allow more cases of undef shuffle indices and add tests for them.
2010-08-17 05:54:34 +00:00
vuzp.ll
Allow more cases of undef shuffle indices and add tests for them.
2010-08-17 05:54:34 +00:00
vzip.ll
Allow more cases of undef shuffle indices and add tests for them.
2010-08-17 05:54:34 +00:00
weak2.ll
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weak.ll
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