llvm-6502/lib/Target/Sparc
Venkatraman Govindaraju eb2aa096bb Generate section for bss and enable weak symbols
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80121 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-26 18:24:12 +00:00
..
AsmPrinter rename TAI -> MAI, being careful not to make MAILJMP instructions :) 2009-08-22 21:43:10 +00:00
TargetInfo Normalize target registration code. 2009-07-31 18:16:53 +00:00
CMakeLists.txt Forgot to update some CMakeLists. 2009-08-22 22:20:11 +00:00
DelaySlotFiller.cpp Remove non-DebugLoc versions of buildMI from Sparc. 2009-02-13 02:31:35 +00:00
FPMover.cpp remove various std::ostream version of printing methods from 2009-08-23 03:41:05 +00:00
Makefile Add TargetInfo libraries for all targets. 2009-07-15 06:35:19 +00:00
README.txt fix CodeGen/Generic/2008-01-25-dag-combine-mul.ll on sparc, PR2105 2008-02-28 05:44:20 +00:00
Sparc.h Add new helpers for registering targets. 2009-07-25 06:49:55 +00:00
Sparc.td Move target independent td files from lib/Target/ to include/llvm/Target so they can be distributed along with the header files. 2008-11-24 07:34:46 +00:00
SparcCallingConv.td Fix a thinko and unbreak sparc default CC 2008-10-10 21:47:37 +00:00
SparcInstrFormats.td Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
SparcInstrInfo.cpp Remove unused member functions. 2009-07-24 07:43:59 +00:00
SparcInstrInfo.h Remove unused member functions. 2009-07-24 07:43:59 +00:00
SparcInstrInfo.td test commit 2009-08-26 04:50:17 +00:00
SparcISelDAGToDAG.cpp Split EVT into MVT and EVT, the former representing _just_ a primitive type, while 2009-08-11 20:47:22 +00:00
SparcISelLowering.cpp Record variable debug info at ISel time directly. 2009-08-22 17:12:53 +00:00
SparcISelLowering.h Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. 2009-08-10 22:56:29 +00:00
SparcMCAsmInfo.cpp Generate section for bss and enable weak symbols 2009-08-26 18:24:12 +00:00
SparcMCAsmInfo.h Rename TargetAsmInfo (and its subclasses) to MCAsmInfo. 2009-08-22 20:48:53 +00:00
SparcRegisterInfo.cpp llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable. 2009-07-14 16:55:14 +00:00
SparcRegisterInfo.h Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo. 2008-03-31 20:40:39 +00:00
SparcRegisterInfo.td Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
SparcSubtarget.cpp Normalize Subtarget constructors to take a target triple string instead of 2009-08-02 22:11:08 +00:00
SparcSubtarget.h Normalize Subtarget constructors to take a target triple string instead of 2009-08-02 22:11:08 +00:00
SparcTargetMachine.cpp Rename TargetAsmInfo (and its subclasses) to MCAsmInfo. 2009-08-22 20:48:53 +00:00
SparcTargetMachine.h Change TargetAsmInfo to be constructed via TargetRegistry from a Target+Triple 2009-08-12 07:22:17 +00:00

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9 
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling 
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for 
  leaf fns.
* Fill delay slots