llvm-6502/lib/CodeGen
Eric Christopher 5cf823cd82 More comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168952 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-29 22:56:13 +00:00
..
AsmPrinter More comment. 2012-11-29 22:56:13 +00:00
SelectionDAG Cleanup recent addition of DAGTypeLegalizer::SplitVecOp_VSELECT 2012-11-29 19:42:09 +00:00
AggressiveAntiDepBreaker.cpp Use MCPhysReg for RegisterClassInfo allocation orders. 2012-11-29 03:34:17 +00:00
AggressiveAntiDepBreaker.h
AllocationOrder.cpp Use MCPhysReg for RegisterClassInfo allocation orders. 2012-11-29 03:34:17 +00:00
AllocationOrder.h Use MCPhysReg for RegisterClassInfo allocation orders. 2012-11-29 03:34:17 +00:00
Analysis.cpp Move the Attributes::Builder outside of the Attributes class and into its own class named AttrBuilder. No functionality change. 2012-10-15 20:35:56 +00:00
AntiDepBreaker.h
BranchFolding.cpp Remove unneeded #include. 2012-11-27 02:00:27 +00:00
BranchFolding.h
CalcSpillWeights.cpp Remove LIS::isAllocatable() and isReserved() helpers. 2012-10-15 22:14:34 +00:00
CallingConvLower.cpp Add newlines to end of debug messages. 2012-11-14 05:20:09 +00:00
CMakeLists.txt Move the guts of TargetInstrInfoImpl into the TargetInstrInfo class. 2012-11-28 02:35:13 +00:00
CodeGen.cpp Add a MachinePostDominator pass 2012-09-17 14:08:37 +00:00
CodePlacementOpt.cpp Create enums for the different attributes. 2012-10-09 07:45:08 +00:00
CriticalAntiDepBreaker.cpp Use MCPhysReg for RegisterClassInfo allocation orders. 2012-11-29 03:34:17 +00:00
CriticalAntiDepBreaker.h
DeadMachineInstructionElim.cpp Switch most getReservedRegs() clients to the MRI equivalent. 2012-10-15 21:57:41 +00:00
DFAPacketizer.cpp
DwarfEHPrepare.cpp
EarlyIfConversion.cpp Stop running the machine code verifier unconditionally. 2012-10-25 00:05:39 +00:00
EdgeBundles.cpp
ExecutionDepsFix.cpp Merge MRI::isPhysRegOrOverlapUsed() into isPhysRegUsed(). 2012-10-17 18:44:18 +00:00
ExpandISelPseudos.cpp
ExpandPostRAPseudos.cpp
GCMetadata.cpp
GCMetadataPrinter.cpp
GCStrategy.cpp Remove GC roots that reference dead objects. 2012-10-26 09:15:55 +00:00
IfConversion.cpp
InlineSpiller.cpp Make the LiveRegMatrix analysis available to targets. 2012-11-28 19:13:06 +00:00
InterferenceCache.cpp
InterferenceCache.h Make the LiveRegMatrix analysis available to targets. 2012-11-28 19:13:06 +00:00
IntrinsicLowering.cpp Revert the series of commits starting with r166578 which introduced the 2012-11-01 08:07:29 +00:00
JITCodeEmitter.cpp
LatencyPriorityQueue.cpp
LexicalScopes.cpp
LiveDebugVariables.cpp Make the LiveRegMatrix analysis available to targets. 2012-11-28 19:13:06 +00:00
LiveDebugVariables.h
LiveInterval.cpp Handle mixed normal and early-clobber defs on inline asm. 2012-11-19 19:31:10 +00:00
LiveIntervalAnalysis.cpp Make the LiveRegMatrix analysis available to targets. 2012-11-28 19:13:06 +00:00
LiveIntervalUnion.cpp Make the LiveRegMatrix analysis available to targets. 2012-11-28 19:13:06 +00:00
LiveRangeCalc.cpp
LiveRangeCalc.h
LiveRangeEdit.cpp Make the LiveRegMatrix analysis available to targets. 2012-11-28 19:13:06 +00:00
LiveRegMatrix.cpp Make the LiveRegMatrix analysis available to targets. 2012-11-28 19:13:06 +00:00
LiveStackAnalysis.cpp Fix a significant recent(?) regression. StackSlotColoring no longer did anything 2012-09-21 20:04:28 +00:00
LiveVariables.cpp Switch most getReservedRegs() clients to the MRI equivalent. 2012-10-15 21:57:41 +00:00
LLVMBuild.txt
LLVMTargetMachine.cpp Fix 80-col violation 2012-11-22 14:10:40 +00:00
LocalStackSlotAllocation.cpp
MachineBasicBlock.cpp Fix physical register liveness calculations: 2012-11-20 09:56:11 +00:00
MachineBlockFrequencyInfo.cpp
MachineBlockPlacement.cpp Create enums for the different attributes. 2012-10-09 07:45:08 +00:00
MachineBranchProbabilityInfo.cpp
MachineCodeEmitter.cpp
MachineCopyPropagation.cpp Remove unneeded #include. 2012-11-27 01:22:15 +00:00
MachineCSE.cpp CSE: allow PerformTrivialCoalescing to check copies across basic block 2012-11-27 18:58:41 +00:00
MachineDominators.cpp
MachineFunction.cpp Revert the majority of the next patch in the address space series: 2012-11-01 09:14:31 +00:00
MachineFunctionAnalysis.cpp
MachineFunctionPass.cpp
MachineFunctionPrinterPass.cpp Symbol hygiene: Make sure declarations and definitions match, make helper functions static. 2012-10-20 12:53:26 +00:00
MachineInstr.cpp Check that iterator I is not the end iterator. 2012-10-31 00:50:52 +00:00
MachineInstrBundle.cpp Fix physical register liveness calculations: 2012-11-20 09:56:11 +00:00
MachineLICM.cpp
MachineLoopInfo.cpp Release build: guard dump functions with 2012-09-11 22:23:19 +00:00
MachineModuleInfo.cpp Move TargetData to DataLayout. 2012-10-08 16:38:25 +00:00
MachineModuleInfoImpls.cpp Rename virtual table anchors from Anchor() to anchor() for consistency with the rest of the tree. 2012-09-26 06:36:36 +00:00
MachinePassRegistry.cpp
MachinePostDominators.cpp Add a MachinePostDominator pass 2012-09-17 14:08:37 +00:00
MachineRegisterInfo.cpp Revert r168630, r168631, and r168633 as these are causing nightly test failures. 2012-11-28 00:21:29 +00:00
MachineScheduler.cpp misched: Recompute priority queue when DFSResults are updated. 2012-11-29 14:36:26 +00:00
MachineSink.cpp Remove unused BitVectors from getAllocatableSet(). 2012-10-16 00:05:06 +00:00
MachineSSAUpdater.cpp
MachineTraceMetrics.cpp Pass an explicit operand number to addLiveIns. 2012-10-11 16:46:07 +00:00
MachineTraceMetrics.h Pass an explicit operand number to addLiveIns. 2012-10-11 16:46:07 +00:00
MachineVerifier.cpp [inline asm] Implement mayLoad and mayStore for inline assembly. In general, 2012-10-30 19:11:54 +00:00
Makefile
OcamlGC.cpp
OptimizePHIs.cpp
Passes.cpp Move else onto line with preceding closing brace. 2012-11-19 00:11:50 +00:00
PeepholeOptimizer.cpp Make sure we iterate over newly created instructions. Fixes pr13625. Testcase to 2012-10-15 18:21:07 +00:00
PHIElimination.cpp
PHIEliminationUtils.cpp
PHIEliminationUtils.h
PostRASchedulerList.cpp misched: Don't consider artificial edges weak edges. 2012-11-13 02:35:06 +00:00
ProcessImplicitDefs.cpp
PrologEpilogInserter.cpp Remove dead code. 2012-11-14 20:25:37 +00:00
PrologEpilogInserter.h
PseudoSourceValue.cpp
README.txt
RegAllocBase.cpp Make the LiveRegMatrix analysis available to targets. 2012-11-28 19:13:06 +00:00
RegAllocBase.h Make the LiveRegMatrix analysis available to targets. 2012-11-28 19:13:06 +00:00
RegAllocBasic.cpp Make the LiveRegMatrix analysis available to targets. 2012-11-28 19:13:06 +00:00
RegAllocFast.cpp Use MCPhysReg for RegisterClassInfo allocation orders. 2012-11-29 03:34:17 +00:00
RegAllocGreedy.cpp Make the LiveRegMatrix analysis available to targets. 2012-11-28 19:13:06 +00:00
RegAllocPBQP.cpp Make the LiveRegMatrix analysis available to targets. 2012-11-28 19:13:06 +00:00
RegisterClassInfo.cpp Use MCPhysReg for RegisterClassInfo allocation orders. 2012-11-29 03:34:17 +00:00
RegisterCoalescer.cpp Avoid rewriting instructions twice. 2012-11-29 00:26:11 +00:00
RegisterCoalescer.h
RegisterPressure.cpp misched: handle on-the-fly regpressure queries better for 2-addr 2012-11-07 07:05:05 +00:00
RegisterScavenging.cpp Remove unneeded #includes. 2012-11-26 21:04:19 +00:00
ScheduleDAG.cpp misched: Don't consider artificial edges weak edges. 2012-11-13 02:35:06 +00:00
ScheduleDAGInstrs.cpp misched: Analysis that partitions the DAG into subtrees. 2012-11-28 05:13:28 +00:00
ScheduleDAGPrinter.cpp
ScoreboardHazardRecognizer.cpp Release build: guard dump functions with 2012-09-11 22:23:19 +00:00
ShadowStackGC.cpp
ShrinkWrapping.cpp
SjLjEHPrepare.cpp Move TargetData to DataLayout. 2012-10-08 16:38:25 +00:00
SlotIndexes.cpp Release build: guard dump functions with 2012-09-11 22:23:19 +00:00
Spiller.cpp Make the LiveRegMatrix analysis available to targets. 2012-11-28 19:13:06 +00:00
Spiller.h
SpillPlacement.cpp
SpillPlacement.h
SplitKit.cpp Make the LiveRegMatrix analysis available to targets. 2012-11-28 19:13:06 +00:00
SplitKit.h
StackColoring.cpp Use std::stable_sort instead of std::sort when sorting stack slots 2012-11-15 19:33:30 +00:00
StackProtector.cpp Create enums for the different attributes. 2012-10-09 07:45:08 +00:00
StackSlotColoring.cpp Fix a significant recent(?) regression. StackSlotColoring no longer did anything 2012-09-21 20:04:28 +00:00
StrongPHIElimination.cpp
TailDuplication.cpp Create enums for the different attributes. 2012-10-09 07:45:08 +00:00
TargetFrameLoweringImpl.cpp
TargetInstrInfo.cpp Move the guts of TargetInstrInfoImpl into the TargetInstrInfo class. 2012-11-28 02:35:13 +00:00
TargetLoweringObjectFileImpl.cpp Use TARGET2 relocation for TType references on ARM. 2012-11-14 01:47:00 +00:00
TargetOptionsImpl.cpp
TargetRegisterInfo.cpp Move Target{Instr,Register}Info.cpp into lib/CodeGen. 2012-11-28 02:35:09 +00:00
TargetSchedule.cpp misched: TargetSchedule interface for machine resources. 2012-11-06 07:10:38 +00:00
TwoAddressInstructionPass.cpp Reduce indentation with early exit. 2012-10-26 23:05:13 +00:00
UnreachableBlockElim.cpp
VirtRegMap.cpp Make the LiveRegMatrix analysis available to targets. 2012-11-28 19:13:06 +00:00

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelihood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvements:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.