llvm-6502/lib/CodeGen
Chad Rosier f496deaa03 Typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157195 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-21 17:13:41 +00:00
..
AsmPrinter Refactor data-in-code annotations. 2012-05-18 19:12:01 +00:00
SelectionDAG Typo. 2012-05-21 17:13:41 +00:00
AggressiveAntiDepBreaker.cpp Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass(). 2012-05-07 22:10:26 +00:00
AggressiveAntiDepBreaker.h
AllocationOrder.cpp Use uint16_t instead of unsigned to store registers in reg classes. Reduces static data size. 2012-03-04 10:16:38 +00:00
AllocationOrder.h Fix old doxygen comment. 2012-01-24 18:09:18 +00:00
Analysis.cpp Fix a long standing tail call optimization bug. When a libcall is emitted 2012-04-10 01:51:00 +00:00
AntiDepBreaker.h
BranchFolding.cpp This patch fixes a problem which arose when using the Post-RA scheduler 2012-04-23 21:39:35 +00:00
BranchFolding.h
CalcSpillWeights.cpp
CallingConvLower.cpp Use uint16_t to store register overlaps to reduce static data. 2012-03-04 10:43:23 +00:00
CMakeLists.txt cmake: new file 2012-04-24 18:06:49 +00:00
CodeGen.cpp Codegen pass definition cleanup. No functionality. 2012-02-08 21:23:13 +00:00
CodePlacementOpt.cpp Codegen pass definition cleanup. No functionality. 2012-02-08 21:23:13 +00:00
CriticalAntiDepBreaker.cpp Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass(). 2012-05-07 22:10:26 +00:00
CriticalAntiDepBreaker.h CriticalAntiDepBreaker: Replace a SmallSet of regs with a much denser BitVector. 2012-03-17 20:22:57 +00:00
DeadMachineInstructionElim.cpp Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce static data size. 2012-03-05 05:37:41 +00:00
DFAPacketizer.cpp Target independent Hexagon Packetizer fix. 2012-05-01 21:28:30 +00:00
DwarfEHPrepare.cpp Relax the requirement that the exception object must be an instruction. During 2012-05-17 17:59:51 +00:00
EdgeBundles.cpp
ExecutionDepsFix.cpp Use uint16_t to store register overlaps to reduce static data. 2012-03-04 10:43:23 +00:00
ExpandISelPseudos.cpp Codegen pass definition cleanup. No functionality. 2012-02-08 21:23:13 +00:00
ExpandPostRAPseudos.cpp Codegen pass definition cleanup. No functionality. 2012-02-08 21:23:13 +00:00
GCMetadata.cpp Add 'llvm_unreachable' to passify GCC's understanding of the constraints 2012-01-10 18:08:01 +00:00
GCMetadataPrinter.cpp
GCStrategy.cpp Remove dead code. Improve llvm_unreachable text. Simplify some control flow. 2012-02-19 11:37:01 +00:00
IfConversion.cpp Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce static data size. 2012-03-05 05:37:41 +00:00
InlineSpiller.cpp Use LiveRangeQuery instead of getLiveRangeContaining(). 2012-05-20 02:44:33 +00:00
InterferenceCache.cpp Use uint16_t to store register overlaps to reduce static data. 2012-03-04 10:43:23 +00:00
InterferenceCache.h Add register mask support to InterferenceCache. 2012-02-10 18:58:34 +00:00
IntrinsicLowering.cpp Remove the now-dead llvm.eh.exception and llvm.eh.selector intrinsics. 2012-01-31 01:58:48 +00:00
JITCodeEmitter.cpp Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch 2011-12-20 02:50:00 +00:00
LatencyPriorityQueue.cpp misched preparation: rename core scheduler methods for consistency. 2012-03-07 23:00:49 +00:00
LexicalScopes.cpp Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch 2011-12-20 02:50:00 +00:00
LiveDebugVariables.cpp Handle NewReg==OldReg in renameRegister(). 2012-05-15 22:20:27 +00:00
LiveDebugVariables.h
LiveInterval.cpp Run proper recursive dead code elimination during coalescing. 2012-05-19 05:25:50 +00:00
LiveIntervalAnalysis.cpp LiveRangeQuery simplifies shrinkToUses(). 2012-05-20 02:54:52 +00:00
LiveIntervalUnion.cpp Oops - LiveIntervalUnion.cpp file does use std::find. Moving STL header include to LiveIntervalUnion.cpp file. 2011-12-21 20:16:11 +00:00
LiveIntervalUnion.h Remove disused STL header include. 2011-12-21 20:12:54 +00:00
LiveRangeCalc.cpp Don't store COPY pointers in VNInfo. 2012-02-04 05:20:49 +00:00
LiveRangeCalc.h
LiveRangeEdit.cpp Fix 12892. 2012-05-19 23:34:59 +00:00
LiveStackAnalysis.cpp
LiveVariables.cpp Fix typo. 2012-04-01 19:27:25 +00:00
LLVMBuild.txt
LLVMTargetMachine.cpp Plug a leak when using MCJIT. 2012-05-20 17:24:08 +00:00
LocalStackSlotAllocation.cpp Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass(). 2012-05-07 22:10:26 +00:00
MachineBasicBlock.cpp MachineBasicBlock::SplitCriticalEdge() should follow LLVM IR variant and refuse to break edge to EH landing pad. rdar://11300144 2012-04-24 19:06:55 +00:00
MachineBlockFrequencyInfo.cpp Add some constantness to BranchProbabilityInfo and BlockFrequnencyInfo. 2011-12-20 20:03:10 +00:00
MachineBlockPlacement.cpp Add a somewhat hacky heuristic to do something different from whole-loop 2012-04-16 13:33:36 +00:00
MachineBranchProbabilityInfo.cpp Add some constantness to BranchProbabilityInfo and BlockFrequnencyInfo. 2011-12-20 20:03:10 +00:00
MachineCodeEmitter.cpp Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch 2011-12-20 02:50:00 +00:00
MachineCopyPropagation.cpp Use a SmallVector and linear lookup instead of a DenseSet - SourceMap values 2012-03-27 19:10:45 +00:00
MachineCSE.cpp Use uint16_t to store register overlaps to reduce static data. 2012-03-04 10:43:23 +00:00
MachineDominators.cpp
MachineFunction.cpp Teach CodeGen's version of computeMaskedBits to understand the range metadata. 2012-03-31 18:14:00 +00:00
MachineFunctionAnalysis.cpp
MachineFunctionPass.cpp
MachineFunctionPrinterPass.cpp
MachineInstr.cpp Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass(). 2012-05-07 22:10:26 +00:00
MachineInstrBundle.cpp Avoid finalizeBundles infinite looping. 2012-03-06 02:00:52 +00:00
MachineLICM.cpp Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass(). 2012-05-07 22:10:26 +00:00
MachineLoopInfo.cpp
MachineLoopRanges.cpp
MachineModuleInfo.cpp Properly emit _fltused with FastISel. Refactor to share code with SDAG. 2012-02-22 19:06:13 +00:00
MachineModuleInfoImpls.cpp
MachinePassRegistry.cpp Allow targets to select the default scheduler by name. 2012-04-19 01:34:10 +00:00
MachineRegisterInfo.cpp Add an MRI::tracksLiveness() flag. 2012-03-27 15:13:58 +00:00
MachineScheduler.cpp comments 2012-05-17 22:37:09 +00:00
MachineSink.cpp Codegen pass definition cleanup. No functionality. 2012-02-08 21:23:13 +00:00
MachineSSAUpdater.cpp More dead code removal (using -Wunreachable-code) 2012-01-20 21:51:11 +00:00
MachineVerifier.cpp Fix a verifier bug. 2012-05-17 18:32:40 +00:00
Makefile
OcamlGC.cpp
OptimizePHIs.cpp Codegen pass definition cleanup. No functionality. 2012-02-08 21:23:13 +00:00
Passes.cpp Change the PassManager from a reference to a pointer. 2012-05-01 08:27:43 +00:00
PeepholeOptimizer.cpp Constrain regclasses in PeepholeOptimizer. 2012-05-20 18:42:55 +00:00
PHIElimination.cpp RegAlloc superpass: includes phi elimination, coalescing, and scheduling. 2012-02-10 04:10:36 +00:00
PHIEliminationUtils.cpp
PHIEliminationUtils.h
PostRASchedulerList.cpp This patch fixes a problem which arose when using the Post-RA scheduler 2012-04-23 21:39:35 +00:00
ProcessImplicitDefs.cpp Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce static data size. 2012-03-05 05:37:41 +00:00
PrologEpilogInserter.cpp Use uint16_t to store registers in callee saved register tables to reduce size of static data. 2012-03-04 03:33:22 +00:00
PrologEpilogInserter.h Codegen pass definition cleanup. No functionality. 2012-02-08 21:23:13 +00:00
PseudoSourceValue.cpp More dead code removal (using -Wunreachable-code) 2012-01-20 21:51:11 +00:00
README.txt
RegAllocBase.cpp Don't look for empty live ranges in the unions. 2012-05-12 00:33:28 +00:00
RegAllocBase.h Make data structures private. 2012-01-11 23:19:08 +00:00
RegAllocBasic.cpp Allow LiveRangeEdit to be created with a NULL parent. 2012-05-19 05:25:46 +00:00
RegAllocFast.cpp Don't access MO reference after invalidating operand list. 2012-05-14 21:30:58 +00:00
RegAllocGreedy.cpp Allow LiveRangeEdit to be created with a NULL parent. 2012-05-19 05:25:46 +00:00
RegAllocPBQP.cpp Allow LiveRangeEdit to be created with a NULL parent. 2012-05-19 05:25:46 +00:00
RegisterClassInfo.cpp Use uint16_t to store register overlaps to reduce static data. 2012-03-04 10:43:23 +00:00
RegisterClassInfo.h Use uint16_t to store registers in callee saved register tables to reduce size of static data. 2012-03-04 03:33:22 +00:00
RegisterCoalescer.cpp Clear kill flags on the fly when joining intervals. 2012-05-20 21:41:05 +00:00
RegisterCoalescer.h Extend the CoalescerPair interface to handle symmetric sub-register copies. 2012-05-15 20:09:43 +00:00
RegisterPressure.cpp misched: Added 3-level regpressure back-off. 2012-05-17 18:35:10 +00:00
RegisterPressure.h misched: Added 3-level regpressure back-off. 2012-05-17 18:35:10 +00:00
RegisterScavenging.cpp Add an MRI::tracksLiveness() flag. 2012-03-27 15:13:58 +00:00
RenderMachineFunction.cpp Fix typo in ruler. No functionality change. 2012-01-03 18:22:43 +00:00
RenderMachineFunction.h
ScheduleDAG.cpp misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles. 2012-03-07 05:21:52 +00:00
ScheduleDAGInstrs.cpp Use LiveRangeQuery in ScheduleDAGInstrs. 2012-05-20 02:44:38 +00:00
ScheduleDAGPrinter.cpp Cleanup in preparation for misched: Move DAG visualization logic. 2012-03-07 00:18:22 +00:00
ScoreboardHazardRecognizer.cpp Remove unnecessary default cases in switches that cover all enum values. 2012-01-10 16:47:17 +00:00
ShadowStackGC.cpp [unwind removal] We no longer have 'unwind' instructions being generated, so 2012-02-06 21:16:41 +00:00
ShrinkWrapping.cpp Expose TargetPassConfig to PEI Pass 2012-02-06 22:51:18 +00:00
SjLjEHPrepare.cpp Revert r152705, which reapplied r152486 as this appears to be causing failures 2012-03-16 01:04:00 +00:00
SlotIndexes.cpp Remove more dead code. 2012-04-25 18:01:30 +00:00
Spiller.cpp Moved LiveRangeEdit.h so that it can be called from other parts of the backend, not just libCodeGen 2012-04-02 22:44:18 +00:00
Spiller.h Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch 2011-12-20 02:50:00 +00:00
SpillPlacement.cpp Give a small negative bias to giant edge bundles. 2012-05-21 03:11:23 +00:00
SpillPlacement.h
SplitKit.cpp Moved LiveRangeEdit.h so that it can be called from other parts of the backend, not just libCodeGen 2012-04-02 22:44:18 +00:00
SplitKit.h Make SplitAnalysis::UseSlots private. 2012-01-12 17:53:44 +00:00
StackProtector.cpp
StackSlotColoring.cpp StackSlotColoring does not use a VirtRegMap 2012-02-21 04:51:19 +00:00
StrongPHIElimination.cpp Remove dead code. Improve llvm_unreachable text. Simplify some control flow. 2012-02-19 11:37:01 +00:00
TailDuplication.cpp Constrain register classes in TailDup. 2012-05-20 18:42:51 +00:00
TargetFrameLoweringImpl.cpp Move parts of lib/Target that use CodeGen into lib/CodeGen. 2011-12-15 22:58:58 +00:00
TargetInstrInfoImpl.cpp Fixed commuteInstructions bug where if its called pre-regalloc the subreg indices weren't commuted 2012-03-28 17:02:22 +00:00
TargetLoweringObjectFileImpl.cpp Look for the 'Is Simulated' module flag. This indicates that the program is compiled to run on a simulator. 2012-04-24 11:03:50 +00:00
TargetOptionsImpl.cpp Move parts of lib/Target that use CodeGen into lib/CodeGen. 2011-12-15 22:58:58 +00:00
TwoAddressInstructionPass.cpp Properly constrain register classes in 2-addr. 2012-05-20 06:38:32 +00:00
UnreachableBlockElim.cpp
VirtRegMap.cpp Transfer regmasks to MRI. 2012-02-17 19:07:56 +00:00
VirtRegMap.h

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelihood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvements:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.