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llvm-6502/lib/Target/PowerPC
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Nate Begeman 73bfa71524 Remove the X86 and PowerPC Simple instruction selectors; their time has 
passed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22886 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-18 23:53:15 +00:00
..
.cvsignore ignore generated files. 2004-11-21 00:00:54 +00:00
LICENSE.TXT Added Louis Gerbarg. Louis is given credit in the CREDITS.TXT file, so I 2004-08-05 23:46:27 +00:00
Makefile Remove support for 64b PPC, it's been broken for a long time. It'll be 2005-08-13 05:59:16 +00:00
PowerPC.td Factor out common .td file chunks. 2004-12-16 16:31:57 +00:00
PowerPCInstrInfo.h Remove trailing whitespace 2005-04-21 23:30:14 +00:00
PowerPCTargetMachine.h Add Subtarget support to PowerPC. Next up, using it. 2005-08-04 07:12:09 +00:00
PPC32.td Factor out common .td file chunks. 2004-12-16 16:31:57 +00:00
PPC32JITInfo.h update interface 2005-07-22 20:49:37 +00:00
PPC32RegisterInfo.td Use the new subtarget support to automatically choose the correct ABI 2005-08-04 20:49:48 +00:00
PPC64.td Factor out common .td file chunks. 2004-12-16 16:31:57 +00:00
PPC64RegisterInfo.td Use the new subtarget support to automatically choose the correct ABI 2005-08-04 20:49:48 +00:00
PPC.h Remove the X86 and PowerPC Simple instruction selectors; their time has 2005-08-18 23:53:15 +00:00
PPCAsmPrinter.cpp Consolidate the GPOpt stuff to all use the Subtarget, instead of still 2005-08-05 22:05:03 +00:00
PPCBranchSelector.cpp Eliminate all remaining tabs and trailing spaces. 2005-07-27 06:12:32 +00:00
PPCCodeEmitter.cpp Eliminate all remaining tabs and trailing spaces. 2005-07-27 06:12:32 +00:00
PPCFrameInfo.h Remove trailing whitespace 2005-04-21 23:30:14 +00:00
PPCInstrBuilder.h Remove trailing whitespace 2005-04-21 23:30:14 +00:00
PPCInstrFormats.td Fix JIT encoding of ppc mfocrf instruction; the operands were reversed 2005-08-08 20:04:52 +00:00
PPCInstrInfo.cpp Remove trailing whitespace 2005-04-21 23:30:14 +00:00
PPCInstrInfo.h Remove trailing whitespace 2005-04-21 23:30:14 +00:00
PPCInstrInfo.td Fix operand numbers by marking variable arity nodes as such and by fixing 2005-08-18 23:25:33 +00:00
PPCISelDAGToDAG.cpp Add shifts. 2005-08-18 23:38:00 +00:00
PPCISelLowering.cpp Make UINT_TO_FP and SINT_TO_FP use generic expansion. 2005-08-17 00:40:22 +00:00
PPCISelLowering.h Pull the LLVM -> DAG lowering code out of the pattern selector so that it 2005-08-16 17:14:42 +00:00
PPCISelPattern.cpp MFLR doesn't take an operand, the LR register is implicit 2005-08-18 23:24:50 +00:00
PPCJITInfo.cpp update interface 2005-07-22 20:49:37 +00:00
PPCJITInfo.h turn off GOT on archs that didn't use it (not that it appeard to harm them much with it on) 2005-07-29 23:32:02 +00:00
PPCRegisterInfo.cpp MFLR doesn't take an operand, the LR register is implicit 2005-08-18 23:24:50 +00:00
PPCRegisterInfo.h Remove trailing whitespace 2005-04-21 23:30:14 +00:00
PPCRegisterInfo.td Revamp the Register class, and allow the use of the RegisterGroup class to 2004-09-14 04:17:02 +00:00
PPCRelocations.h Eliminate tabs and trailing spaces. 2005-07-27 05:53:44 +00:00
PPCSubtarget.cpp Consolidate the GPOpt stuff to all use the Subtarget, instead of still 2005-08-05 22:05:03 +00:00
PPCSubtarget.h Consolidate the GPOpt stuff to all use the Subtarget, instead of still 2005-08-05 22:05:03 +00:00
PPCTargetMachine.cpp Remove the X86 and PowerPC Simple instruction selectors; their time has 2005-08-18 23:53:15 +00:00
PPCTargetMachine.h Remove trailing whitespace 2005-04-21 23:30:14 +00:00
README.txt Make FP_TO_UINT Illegal. This allows us to generate significantly better 2005-08-14 01:17:16 +00:00

README.txt 

TODO:
* gpr0 allocation
* implement do-loop -> bdnz transform
* implement powerpc-64 for darwin
* use stfiwx in float->int
* be able to combine sequences like the following into 2 instructions:
	lis r2, ha16(l2__ZTV4Cell)
	la r2, lo16(l2__ZTV4Cell)(r2)
	addi r2, r2, 8

* Teach LLVM how to codegen this:
unsigned short foo(float a) { return a; }
as:
_foo:
        fctiwz f0,f1
        stfd f0,-8(r1)
        lhz r3,-2(r1)
        blr
not:
_foo:
        fctiwz f0, f1
        stfd f0, -8(r1)
        lwz r2, -4(r1)
        rlwinm r3, r2, 0, 16, 31
        blr


* Support 'update' load/store instructions.  These are cracked on the G5, but
  are still a codesize win.

* Add a custom legalizer for the GlobalAddress node, to move the funky darwin
  stub stuff from the instruction selector to the legalizer (exposing low-level
  operations to the dag for optzn.  For example, we want to codegen this:

        int A = 0;
        void B() { A++; }
  as:
        lis r9,ha16(_A)
        lwz r2,lo16(_A)(r9)
        addi r2,r2,1
        stw r2,lo16(_A)(r9)
  not:
        lis r2, ha16(_A)
        lwz r2, lo16(_A)(r2)
        addi r2, r2, 1
        lis r3, ha16(_A)
        stw r2, lo16(_A)(r3)

* should hint to the branch select pass that it doesn't need to print the
  second unconditional branch, so we don't end up with things like:
	b .LBBl42__2E_expand_function_8_674	; loopentry.24
	b .LBBl42__2E_expand_function_8_42	; NewDefault
	b .LBBl42__2E_expand_function_8_42	; NewDefault