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596 Commits

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Author SHA1 Message Date
Karol Stasiak
8dd8415432 6502: Track values of zeropage registers 2018-08-07 21:36:53 +02:00
Karol Stasiak
64744f7559 Fix initialized array allocation 2018-08-07 19:50:02 +02:00
Karol Stasiak
8dfb223a8c Fast memset for Z80 and 6502 2018-08-07 17:37:09 +02:00
Karol Stasiak
7750c4ec45 Optimize constants of form (B+A)-B 2018-08-07 17:36:14 +02:00
Karol Stasiak
f937355c54 6502: Fix word addition if zpreg is larger than 2 2018-08-07 17:35:40 +02:00
Karol Stasiak
3e7bbaf5fc Z80: optimize loads to registers pairs 2018-08-07 17:35:02 +02:00
Karol Stasiak
a8f6bc4c0e Z80: Correctly analyze flow through LDIR and LDDR 2018-08-07 17:34:31 +02:00
Karol Stasiak
c846a19eef Preliminary support for object alignment 2018-08-07 17:32:20 +02:00
Karol Stasiak
60d2cc1959 Actually enable code decuplication 2018-08-07 17:28:59 +02:00
Karol Stasiak
ff16854a11 Code deduplication 2018-08-06 19:29:09 +02:00
Karol Stasiak
f045f7f4c2 Z80: Analyze flow through RES and SET correctly 2018-08-06 19:20:07 +02:00
Karol Stasiak
86ce1d42f3 6502: More optimizations. 2018-08-06 19:19:13 +02:00
Karol Stasiak
87c5d698bc 6502: Don't optimize away things like a[f()]^=0 2018-08-06 19:17:57 +02:00
Karol Stasiak
a2eb6fe353 Z80: fix subtraction. 2018-08-06 19:17:08 +02:00
Karol Stasiak
7cf78ca2bd Use one statement preprocessor per function. 2018-08-06 19:16:42 +02:00
Karol Stasiak
bf47473162 Allow setting the size of the zeropage register from the command line. 2018-08-06 19:15:41 +02:00
Karol Stasiak
516b44ad05 Add docs about Intel asm syntax 2018-08-03 17:26:26 +02:00
Karol Stasiak
75c9e09e97 Updated UDL syntax 2018-08-03 17:08:25 +02:00
Karol Stasiak
48b183828b Z80: LDH instruction for LR35902 2018-08-03 16:43:31 +02:00
Karol Stasiak
f4a2c96512 Fix comparisons 2018-08-03 16:21:02 +02:00
Karol Stasiak
fab1cafec3 Z80: Intel syntax support 2018-08-03 13:23:37 +02:00
Karol Stasiak
e393a3de9c Z80: More optimizations 2018-08-03 13:21:04 +02:00
Karol Stasiak
388ceb8b3a 6502: software BCD, increase default zpreg to 4 2018-08-03 13:06:23 +02:00
Karol Stasiak
30aa62ceaf Z80: Fix 16-bit operations 2018-08-03 13:02:18 +02:00
Karol Stasiak
a8ab3b2c3f Documentation update 2018-08-03 13:00:52 +02:00
Karol Stasiak
779cc6ab5c Extract asDecimal. Improve constants. 2018-08-03 12:59:44 +02:00
Karol Stasiak
0a01dd30e1 6502: Fix zeropage register if larger than 2 bytes 2018-08-03 11:11:03 +02:00
Karol Stasiak
e952d89849 Z80: Intel syntax for output. 2018-08-01 21:16:20 +02:00
Karol Stasiak
d4beba11a1 Z80: >>' operator 2018-08-01 18:49:37 +02:00
Karol Stasiak
107474978e Updated reentrancy documentation 2018-08-01 18:49:15 +02:00
Karol Stasiak
9b5b39181a Z80: Decimal subtraction on 8080, fixes for adding longs returned from functions 2018-08-01 15:33:07 +02:00
Karol Stasiak
6b02c5178a Z80: More arithmetic optimizations 2018-08-01 15:32:11 +02:00
Karol Stasiak
0326c7a73b Z80: Fix stack-related optimizations 2018-08-01 15:31:42 +02:00
Karol Stasiak
bc1dc0e500 6502: allow functions with large return values on the right hand side of modifying operators 2018-08-01 15:28:47 +02:00
Karol Stasiak
69f233e378 Z80: Interrupt handlers. Allow using IY as base pointer. 2018-08-01 12:50:05 +02:00
Karol Stasiak
99df25bde2 Fix macro expansion 2018-08-01 12:43:17 +02:00
Karol Stasiak
ffbed1ba26 Allow processed/formatted array contents inside other array literals 2018-08-01 10:34:49 +02:00
Karol Stasiak
bebb8c45a5 Z80: More optimizations 2018-08-01 10:22:34 +02:00
Karol Stasiak
ec9dba9d27 Z80: Use RRA instead of RR A in stdlib 2018-08-01 10:16:20 +02:00
Karol Stasiak
e914ad6d7b Move label generation into a separate class 2018-07-31 18:16:36 +02:00
Karol Stasiak
f929e396df Preliminary CP/M support 2018-07-31 01:02:55 +02:00
Karol Stasiak
2046f94b55 Z80: Compile 8-bit values directly into registers other than A 2018-07-31 01:00:17 +02:00
Karol Stasiak
7e6f2dd4ea Z80: CALL <number> shouldn't prevent inlining 2018-07-31 00:59:24 +02:00
Karol Stasiak
e0bec29318 Minor documentation updates 2018-07-31 00:58:43 +02:00
Karol Stasiak
53f550d266 Z80: Fix line size calculations 2018-07-31 00:52:01 +02:00
Karol Stasiak
2bac42c187 Optimizations for LR35902 and 8080 2018-07-30 23:51:41 +02:00
Karol Stasiak
6d7643b817 6502: Better descriptions of benchmarked tests 2018-07-30 23:50:44 +02:00
Karol Stasiak
453ce93952 Z80: RLA and RL A are two very different instructions 2018-07-30 23:49:25 +02:00
Karol Stasiak
2ef79d6894 Minor improvements for Intel 8080 and ZX Spectrum 2018-07-30 18:55:20 +02:00
Karol Stasiak
998902acf6 Refactor: error logging 2018-07-30 18:53:08 +02:00