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integrate zero-riscy

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This commit is contained in:
marqs
2018-10-06 01:07:53 +03:00
parent e1d8446752
commit 4676cbd2f0
44 changed files with 11897 additions and 9998 deletions
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software/sys_controller/Makefile
+14 -1
View File
@@ -754,6 +754,8 @@ ifeq ($(MKDIR),)
MKDIR := $(DEFAULT_MKDIR)
endif
RV_OBJCOPY = riscv64-unknown-elf-objcopy
#------------------------------------------------------------------------------
# PATTERN RULES TO BUILD OBJECTS
#------------------------------------------------------------------------------
@@ -1127,5 +1129,16 @@ print-elf-name:
ossc/menu_sjis.c: ossc/menu.c
iconv -f UTF-8 -t SHIFT-JIS ossc/menu.c > ossc/menu_sjis.c
mem_init/sys_onchip_memory2_0.hex: sys_controller.elf
$(RV_OBJCOPY) --change-addresses -0x10000 -O binary --gap-fill 0 $< mem_init/sys_onchip_memory2_0.bin
../../tools/bin2hex mem_init/sys_onchip_memory2_0.bin mem_init/sys_onchip_memory2_0.hex
.PHONY: mem_init_generate_new
mem_init_generate_new: mem_init/sys_onchip_memory2_0.hex
.PHONY: generate_hex
generate_hex: clean mem_init_generate
generate_hex: clean mem_init_generate_new
.PHONY: rv-reprogram
rv-reprogram: mem_init_generate_new
system-console -cli --script ../../scripts/rv-reprogram.tcl
software/sys_controller/crt0.boot.S
+103
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@@ -0,0 +1,103 @@
// Copyright 2017 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the “License”); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
#include "pulpino.h"
#define EXCEPTION_STACK_SIZE 72
/* ========================================================= [ entry ] === */
.section .text
default_exc_handler:
jal x0, default_exc_handler
reset_handler:
/* set all registers to zero */
mv x1, x0
mv x2, x1
mv x3, x1
mv x4, x1
mv x5, x1
mv x6, x1
mv x7, x1
mv x8, x1
mv x9, x1
mv x10, x1
mv x11, x1
mv x12, x1
mv x13, x1
mv x14, x1
mv x15, x1
mv x16, x1
mv x17, x1
mv x18, x1
mv x19, x1
mv x20, x1
mv x21, x1
mv x22, x1
mv x23, x1
mv x24, x1
mv x25, x1
mv x26, x1
mv x27, x1
mv x28, x1
mv x29, x1
mv x30, x1
mv x31, x1
/* stack initilization */
la x2, _stack_start
_start:
.global _start
/* clear BSS */
la x26, _bss_start
la x27, _bss_end
bge x26, x27, zero_loop_end
zero_loop:
sw x0, 0(x26)
addi x26, x26, 4
ble x26, x27, zero_loop
zero_loop_end:
main_entry:
/* jump to alt_main program entry point */
jal alt_main
/* =================================================== [ exceptions ] === */
/* This section has to be down here, since we have to disable rvc for it */
.section .vectors, "ax"
.option norvc;
// external interrupts are handled by the same callback
// until compiler supports IRQ routines
.org 0x00
.rept 31
nop
.endr
jal x0, default_exc_handler
// reset vector
.org 0x80
jal x0, reset_handler
// illegal instruction exception
.org 0x84
jal x0, default_exc_handler
// ecall handler
.org 0x88
jal x0, default_exc_handler
software/sys_controller/it6613/hdmitx.h
+1 -1
View File
@@ -52,7 +52,7 @@
//#define NULL 0
//typedef unsigned char bool;
#include "Altera_UP_SD_Card_Avalon_Interface_mod.h"
typedef unsigned char bool;
#include "sysconfig.h"
// Hardwired to CPU reset
software/sys_controller/link.common.ld
+135
View File
@@ -0,0 +1,135 @@
SEARCH_DIR(.)
__DYNAMIC = 0;
MEMORY
{
dataram : ORIGIN = 0x00010000, LENGTH = 0x9000
}
/* Stack information variables */
_min_stack = 0x400; /* 1K - minimum stack space to reserve */
_stack_start = ORIGIN(dataram) + LENGTH(dataram);
/* We have to align each sector to word boundaries as our current s19->slm
* conversion scripts are not able to handle non-word aligned sections. */
SECTIONS
{
.vectors :
{
. = ALIGN(4);
KEEP(*(.vectors))
} > dataram
.text : {
. = ALIGN(4);
_stext = .;
*(.text)
*(.text.*)
_etext = .;
__CTOR_LIST__ = .;
LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
*(.ctors)
LONG(0)
__CTOR_END__ = .;
__DTOR_LIST__ = .;
LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
*(.dtors)
LONG(0)
__DTOR_END__ = .;
*(.lit)
*(.shdata)
_endtext = .;
} > dataram
/*--------------------------------------------------------------------*/
/* Global constructor/destructor segement */
/*--------------------------------------------------------------------*/
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
} > dataram
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array ))
PROVIDE_HIDDEN (__init_array_end = .);
} > dataram
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array ))
PROVIDE_HIDDEN (__fini_array_end = .);
} > dataram
.rodata : {
. = ALIGN(4);
*(.rodata);
*(.rodata.*)
} > dataram
.shbss :
{
. = ALIGN(4);
*(.shbss)
} > dataram
.data : {
. = ALIGN(4);
sdata = .;
_sdata = .;
*(.data);
*(.data.*)
*(.sdata);
*(.sdata.*)
*(.sdata2);
*(.sdata2.*)
edata = .;
_edata = .;
} > dataram
.bss :
{
. = ALIGN(4);
_bss_start = .;
*(.bss)
*(.bss.*)
*(.sbss)
*(.sbss.*)
*(COMMON)
_bss_end = .;
} > dataram
/* ensure there is enough room for stack */
.stack (NOLOAD): {
. = ALIGN(4);
. = . + _min_stack ;
. = ALIGN(4);
stack = . ;
_stack = . ;
} > dataram
.stab 0 (NOLOAD) :
{
[ .stab ]
}
.stabstr 0 (NOLOAD) :
{
[ .stabstr ]
}
.bss :
{
. = ALIGN(4);
_end = .;
} > dataram
}
software/sys_controller/link.riscv.ld
+7
View File
@@ -0,0 +1,7 @@
/* not needed, but we need separate linker scripts anyway */
OUTPUT_ARCH(riscv)
/* required to correctly link newlib */
GROUP( -lc -lgloss -lgcc -lsupc++ )
INCLUDE link.common.ld
software/sys_controller/mem_init/sys_onchip_memory2_0.hex
+7365 -1281
View File
File diff suppressed because it is too large Load Diff
software/sys_controller/ossc/controls.c
+1 -1
View File
@@ -163,7 +163,7 @@ int parse_control()
((fpga_status >> 16) & 0x3) ? '*' : ' ',
fpga_v_hz_x100/100,
fpga_v_hz_x100%100);*/
sniprintf(menu_row2, LCD_ROW_LEN+1, "%4lu%c%c %u", (((fpga_status & 0x7ff)+1)<<fpga_ilace)+fpga_ilace,
sniprintf(menu_row2, LCD_ROW_LEN+1, "%4lu%c%c %lu", (((fpga_status & 0x7ff)+1)<<fpga_ilace)+fpga_ilace,
fpga_ilace ? 'i' : 'p',
((fpga_status >> 16) & 0x3) ? '*' : ' ',
IORD_ALTERA_AVALON_PIO_DATA(PIO_8_BASE));
software/sys_controller/ossc/firmware.h
+1 -1
View File
@@ -24,7 +24,7 @@
#include "sysconfig.h"
#define FW_VER_MAJOR 0
#define FW_VER_MINOR 81
#define FW_VER_MINOR 82
#ifdef ENABLE_AUDIO
#define FW_SUFFIX1 "a"
software/sys_controller/pulpino.h
+91
View File
@@ -0,0 +1,91 @@
// Copyright 2017 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the “License”); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
/**
* @file
* @brief Register mapping for PULPino peripherals.
*
* Contains event register mappings for the PULPino SOC as
* well as some general definitions for the overall system.
*
* @author Florian Zaruba
*
* @version 1.0
*
* @date 2/10/2015
*
*/
#ifndef PULPINO_H
#define PULPINO_H
#define PULPINO_BASE_ADDR 0x10000000
/** SOC PERIPHERALS */
#define SOC_PERIPHERALS_BASE_ADDR ( PULPINO_BASE_ADDR + 0xA100000 )
#define UART_BASE_ADDR ( SOC_PERIPHERALS_BASE_ADDR + 0x0000 )
#define GPIO_BASE_ADDR ( SOC_PERIPHERALS_BASE_ADDR + 0x1000 )
#define SPI_BASE_ADDR ( SOC_PERIPHERALS_BASE_ADDR + 0x2000 )
#define TIMER_BASE_ADDR ( SOC_PERIPHERALS_BASE_ADDR + 0x3000 )
#define EVENT_UNIT_BASE_ADDR ( SOC_PERIPHERALS_BASE_ADDR + 0x4000 )
#define I2C_BASE_ADDR ( SOC_PERIPHERALS_BASE_ADDR + 0x5000 )
#define FLL_BASE_ADDR ( SOC_PERIPHERALS_BASE_ADDR + 0x6000 )
#define SOC_CTRL_BASE_ADDR ( SOC_PERIPHERALS_BASE_ADDR + 0x7000 )
/** STDOUT */
#define STDOUT_BASE_ADDR ( SOC_PERIPHERALS_BASE_ADDR + 0x10000 )
#define FPUTCHAR_BASE_ADDR ( STDOUT_BASE_ADDR + 0x1000 )
#define FILE_CMD_BASE_ADDR ( STDOUT_BASE_ADDR + 0x2000 )
#define STREAM_BASE_ADDR ( STDOUT_BASE_ADDR + 0x3000 )
/** Instruction RAM */
#define INSTR_RAM_BASE_ADDR ( 0x00 )
#define INSTR_RAM_START_ADDR ( 0x80 )
/** ROM */
#define ROM_BASE_ADDR ( 0x10000 )
/** Data RAM */
#define DATA_RAM_BASE_ADDR ( 0x00100000 )
/** Registers and pointers */
#define REGP(x) ((volatile unsigned int*)(x))
#define REG(x) (*((volatile unsigned int*)(x)))
#define REGP_8(x) (((volatile uint8_t*)(x)))
/* pointer to mem of apb pulpino unit - PointerSocCtrl */
#define __PSC__(a) *(unsigned volatile int*) (SOC_CTRL_BASE_ADDR + a)
/** Peripheral Clock gating */
#define CGREG __PSC__(0x04)
/** Clock gate SPI */
#define CGSPI 0x00
/** Clock gate UART */
#define CGUART 0x01
/** Clock gate GPIO */
#define CGGPIO 0x02
/** Clock gate SPI Master */
#define CGGSPIM 0x03
/** Clock gate Timer */
#define CGTIM 0x04
/** Clock gate Event Unit */
#define CGEVENT 0x05
/** Clock gate I2C */
#define CGGI2C 0x06
/** Clock gate FLL */
#define CGFLL 0x07
/** Boot address register */
#define BOOTREG __PSC__(0x08)
#define RES_STATUS __PSC__(0x14)
#endif