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integrate zero-riscy

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marqs 2018-10-06 01:07:53 +03:00
parent e1d8446752
commit 4676cbd2f0
44 changed files with 11897 additions and 9998 deletions
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[submodule "ip/pulpino_qsys"]
path = ip/pulpino_qsys
url = https://github.com/marqs85/pulpino_qsys.git

56
ip/altera_nios_custom_instr_endianconverter_qsys/endianconverter_qsys.v
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// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module endianconverter_qsys (
// inputs:
dataa,
datab,
// outputs:
result
)
;
output [ 31: 0] result;
input [ 31: 0] dataa;
input [ 31: 0] datab;
wire [ 31: 0] result;
//s1, which is an e_custom_instruction_slave
assign result[7 : 0] = dataa[31 : 24];
assign result[15 : 8] = dataa[23 : 16];
assign result[23 : 16] = dataa[15 : 8];
assign result[31 : 24] = dataa[7 : 0];
endmodule

84
ip/altera_nios_custom_instr_endianconverter_qsys/endianconverter_qsys_hw.tcl
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# (C) 2001-2015 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and other
# software and tools, and its AMPP partner logic functions, and any output
# files any of the foregoing (including device programming or simulation
# files), and any associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License Subscription
# Agreement, Altera MegaCore Function License Agreement, or other applicable
# license agreement, including, without limitation, that your use is for the
# sole purpose of programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the applicable
# agreement for further details.
# TCL File Generated by Component Editor 10.1
# Tue Aug 17 15:04:48 MYT 2010
# DO NOT MODIFY
# +-----------------------------------
# |
# |
# | ./converter_0.v syn, sim
# |
# +-----------------------------------
# +-----------------------------------
# | request TCL package from ACDS 10.1
# |
package require -exact sopc 10.1
# |
# +-----------------------------------
# +-----------------------------------
# | module altera_nios_custom_instr_endian_converter
# |
set_module_property NAME altera_nios_custom_instr_endianconverter
set_module_property VERSION 17.1
set_module_property INTERNAL false
set_module_property GROUP "Custom Instruction Modules"
set_module_property AUTHOR "Altera Corporation"
set_module_property DISPLAY_NAME "Endian Converter"
set_module_property HIDE_FROM_SOPC true
set_module_property TOP_LEVEL_HDL_FILE endianconverter_qsys.v
set_module_property TOP_LEVEL_HDL_MODULE endianconverter_qsys
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property SIMULATION_MODEL_IN_VHDL true
set_module_property EDITABLE false
set_module_property ANALYZE_HDL FALSE
# |
# +-----------------------------------
# +-----------------------------------
# | files
# |
add_file endianconverter_qsys.v {SYNTHESIS SIMULATION}
# |
# +-----------------------------------
# +-----------------------------------
# | parameters
# |
# |
# +-----------------------------------
# +-----------------------------------
# | display items
# |
# |
# +-----------------------------------
# +-----------------------------------
# | connection point s1
# |
add_interface s1 nios_custom_instruction end
set_interface_property s1 clockCycle 1
set_interface_property s1 operands 1
set_interface_property s1 ENABLED true
add_interface_port s1 dataa dataa Input 32
add_interface_port s1 datab datab Input 32
add_interface_port s1 result result Output 32
# |
# +-----------------------------------

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ip/nios2_hw_crc/HAL/doc/crc_main.c
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/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* Altera does not recommend, suggest or require that this reference design *
* file be used in conjunction or combination with any other product. *
******************************************************************************/
/******************************************************************************
* Author - JCJB *
* *
* This design uses the following CRC-32 implementations: *
* *
* --> Software - Uses modulo 2 division to perform the remainder calculation. *
* --> Optimized Software - Uses a lookup table of all possible division *
* values. The calculation operates on 8 bit data. *
* --> Custom Instruction - Uses a parallel hardware CRC circuit to calculate *
* the remainder. The calculation operates on 8, *
* 16, 24, or 32 bit data. *
* *
* The software implementations can be changed to CRC-16 or CRC-CCITT however *
* the custom instruction must be modified as well to support the same *
* standard. Simply use the values defined in crc.h to change the standard *
* used (using the same values in the hardware parameterization) or define *
* your own standard. *
*******************************************************************************/
#include "system.h"
#include "stdio.h"
#include "crc.h"
#include "ci_crc.h"
#include "sys/alt_timestamp.h"
#include "stdlib.h"
/* Modify these values to adjust the test being performed */
#define NUMBER_OF_BUFFERS 32
#define BUFFER_SIZE 256 /* in bytes */
/* Change the name of memory device according to what you are using
* e.g.: DDR_SDRAM_0 ##_SPAN
* SSRAM_0 ##_SPAN
*/
#define MEMORY_DEVICE_SIZE 32768
/* Make sure there is room left for Nios II text, rodata, rwdata, stack,
* and heap. This software and the buffer space must fit within the
* size of memory device. A total of 1.5 MBytes is reserved. If BUFFER_SIZE
* is a multiple of four then exactly 256kB will be left, otherwise is
* amount will be less since the column dimension needs some padding to
* stay 32 bit aligned
*/
#if ((BUFFER_SIZE * NUMBER_OF_BUFFERS) >= MEMORY_DEVICE_SIZE - 10000)
#error Your buffer space has exceeded the maximum allowable space. Please\
reduce the buffer space so that there is enough room to hold Nios II\
code.
#endif
/* This will line up the data onto a 32 bit (or greater) boundary. A 2d array
* is being used here for simplicity. The first dimension represents a byte
* of data and the second dimension represents an individual buffer
*/
#if ((BUFFER_SIZE & 0x3) == 0)
unsigned char data_buffer_region[NUMBER_OF_BUFFERS][BUFFER_SIZE] __attribute__ ((aligned(4)));
#else /* need to allocate extra bytes so that all buffers start on a 32 bit
boundaries by rounding up the column dimension to the next power of 4
*/
unsigned char data_buffer_region[NUMBER_OF_BUFFERS][BUFFER_SIZE + 4 - (BUFFER_SIZE&0x3)] __attribute__ ((aligned(4)));
#endif
int main()
{
unsigned long buffer_counter, data_counter;
unsigned long sw_slow_results[NUMBER_OF_BUFFERS];
unsigned long sw_fast_results[NUMBER_OF_BUFFERS];
unsigned long ci_results[NUMBER_OF_BUFFERS];
unsigned char random_data = 0x5A;
//unsigned long sw_slow_timeA, sw_slow_timeB;
// unsigned long sw_fast_timeA, sw_fast_timeB;
// unsigned long ci_timeA, ci_timeB;
alt_u32 sw_slow_timeA, sw_slow_timeB;
alt_u32 sw_fast_timeA, sw_fast_timeB;
alt_u32 ci_timeA, ci_timeB;
printf("+-----------------------------------------------------------+\n");
printf("| Comparison between software and custom instruction CRC32 |\n");
printf("+-----------------------------------------------------------+\n\n\n");
printf("System specification\n");
printf("--------------------\n");
printf("System clock speed = %lu MHz\n", (unsigned long)ALT_CPU_FREQ /(unsigned long)1000000);
printf("Number of buffer locations = %d\n", NUMBER_OF_BUFFERS);
printf("Size of each buffer = %d bytes\n\n\n", BUFFER_SIZE);
/* Initializing the data buffers */
printf("Initializing all of the buffers with pseudo-random data\n");
printf("-------------------------------------------------------\n");
for(buffer_counter = 0; buffer_counter < NUMBER_OF_BUFFERS; buffer_counter++)
{
for(data_counter = 0; data_counter < BUFFER_SIZE; data_counter++)
{
data_buffer_region[buffer_counter][data_counter] = random_data;
random_data = (random_data >> 4) + (random_data << 4) + (data_counter & 0xFF);
}
}
printf("Initialization completed\n\n\n");
if(alt_timestamp_start() < 0) // starts the timestamp timer
{
printf("Please add the high resolution timer to the timestamp timer setting in the syslib properties page.\n");
exit(1);
}
/* Slow software CRC based on a modulo 2 division implementation */
printf("Running the software CRC\n");
printf("------------------------\n");
sw_slow_timeA = alt_timestamp();
for(buffer_counter = 0; buffer_counter < NUMBER_OF_BUFFERS; buffer_counter++)
{
sw_slow_results[buffer_counter] = crcSlow(data_buffer_region[buffer_counter], BUFFER_SIZE);
}
sw_slow_timeB = alt_timestamp();
printf("Completed\n\n\n");
/* Fast software CRC based on a lookup table implementation */
crcInit();
printf("Running the optimized software CRC\n");
printf("----------------------------------\n");
sw_fast_timeA = alt_timestamp();
for(buffer_counter = 0; buffer_counter < NUMBER_OF_BUFFERS; buffer_counter++)
{
sw_fast_results[buffer_counter] = crcFast(data_buffer_region[buffer_counter], BUFFER_SIZE);
}
sw_fast_timeB = alt_timestamp();
printf("Completed\n\n\n");
/* Custom instruction CRC */
printf("Running the custom instruction CRC\n");
printf("----------------------------------\n");
ci_timeA = alt_timestamp();
for(buffer_counter = 0; buffer_counter < NUMBER_OF_BUFFERS; buffer_counter++)
{
ci_results[buffer_counter] = crcCI(data_buffer_region[buffer_counter], BUFFER_SIZE);
}
ci_timeB = alt_timestamp();
printf("Completed\n\n\n");
/* Validation of results */
printf("Validating the CRC results from all implementations\n");
printf("----------------------------------------------------\n");
for(buffer_counter = 0; buffer_counter < NUMBER_OF_BUFFERS; buffer_counter++)
{
/* Test every combination of results to make sure they are consistant */
if((sw_slow_results[buffer_counter] != ci_results[buffer_counter]) |
(sw_fast_results[buffer_counter] != ci_results[buffer_counter]))
{
printf("FAILURE! Software CRC = 0x%lx, Optimized Software CRC = 0x%lx, Custom Instruction CRC = 0x%lx,\n",
sw_slow_results[buffer_counter], sw_fast_results[buffer_counter], ci_results[buffer_counter]);
exit(1);
}
}
printf("All CRC implementations produced the same results\n\n\n");
// Report processing times
printf("Processing time for each implementation\n");
printf("---------------------------------------\n");
printf("Software CRC = %.2lu ms\n", 1000*((unsigned long)(sw_slow_timeB-sw_slow_timeA))/((unsigned long)alt_timestamp_freq()));
printf("Optimized software CRC = %.2lu ms\n", 1000*((unsigned long)(sw_fast_timeB-sw_fast_timeA))/((unsigned long)alt_timestamp_freq()));
printf("Custom instruction CRC = %.2lu ms\n\n\n", 1000*((unsigned long)(ci_timeB-ci_timeA))/((unsigned long)alt_timestamp_freq()));
printf("Processing throughput for each implementation\n"); // throughput = total bits / (time(s) * 1000000)
printf("---------------------------------------------\n");
printf("Software CRC = %.2lu Mbps\n", (8 * NUMBER_OF_BUFFERS * BUFFER_SIZE)/(1000000*(unsigned long)(sw_slow_timeB-sw_slow_timeA)/((unsigned long)alt_timestamp_freq())));
printf("Optimized software CRC = %.2lu Mbps\n", (8 * NUMBER_OF_BUFFERS * BUFFER_SIZE)/(1000000*(unsigned long)(sw_fast_timeB-sw_fast_timeA)/((unsigned long)alt_timestamp_freq())));
printf("Custom instruction CRC = %.2lu Mbps\n\n\n", (8 * NUMBER_OF_BUFFERS * BUFFER_SIZE)/(1000000*(unsigned long)(ci_timeB-ci_timeA)/((unsigned long)alt_timestamp_freq())));
printf("Speedup ratio\n");
printf("-------------\n");
printf("Custom instruction CRC vs software CRC = %lu\n", ((unsigned long)(sw_slow_timeB-sw_slow_timeA))/((unsigned long)(ci_timeB-ci_timeA)));
printf("Custom instruction CRC vs optimized software CRC = %lu\n", ((unsigned long)(sw_fast_timeB-sw_fast_timeA))/((unsigned long)(ci_timeB-ci_timeA)));
printf("Optimized software CRC vs software CRC= %lu\n", ((unsigned long)(sw_slow_timeB-sw_slow_timeA))/((unsigned long)(sw_fast_timeB-sw_fast_timeA)));
return 0;
}

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ip/nios2_hw_crc/HAL/src/ci_crc.c
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/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* Altera does not recommend, suggest or require that this reference design *
* file be used in conjunction or combination with any other product. *
******************************************************************************/
/**********************************************************************
*
* Filename: ci_crc.c
*
* Description: Custom instruction implementations of the CRC.
*
* Notes: A macro is defined that is used to access the CRC custom
* instruction.
*********************************************************************/
#include "system.h"
/*The n values and their corresponding operation are as follow:
* n = 0, Initialize the custom instruction to the initial remainder value
* n = 1, Write 8 bits data to custom instruction
* n = 2, Write 16 bits data to custom instruction
* n = 3, Write 32 bits data to custom instruction
* n = 4, Read 32 bits data from the custom instruction
* n = 5, Read 64 bits data from the custom instruction
* n = 6, Read 96 bits data from the custom instruction
* n = 7, Read 128 bits data from the custom instruction*/
#define CRC_CI_MACRO(n, A) __builtin_custom_ini(ALT_CI_NIOS2_HW_CRC32_0_N + (n & 0x7), (A))
unsigned long crcCI(unsigned char * input_data, unsigned long input_data_length, int do_initialize)
{
unsigned long index;
/* copy of the data buffer pointer so that it can advance by different widths */
void * input_data_copy = (void *)input_data;
/* The custom instruction CRC will initialize to the inital remainder value */
if (do_initialize)
CRC_CI_MACRO(0,0);
/* Write 32 bit data to the custom instruction. If the buffer does not end
* on a 32 bit boundary then the remaining data will be sent to the custom
* instruction in the 'if' statement below.
*/
for(index = 0; index < (input_data_length & 0xFFFFFFFC); index+=4)
{
CRC_CI_MACRO(3, *(unsigned long *)input_data_copy);
input_data_copy += 4; /* void pointer, must move by 4 for each word */
}
/* Write the remainder of the buffer if it does not end on a word boundary */
if((input_data_length & 0x3) == 0x3) /* 3 bytes left */
{
CRC_CI_MACRO(2, *(unsigned short *)input_data_copy);
input_data_copy += 2;
CRC_CI_MACRO(1, *(unsigned char *)input_data_copy);
}
else if((input_data_length & 0x3) == 0x2) /* 2 bytes left */
{
CRC_CI_MACRO(2, *(unsigned short *)input_data_copy);
}
else if((input_data_length & 0x3) == 0x1) /* 1 byte left */
{
CRC_CI_MACRO(1, *(unsigned char *)input_data_copy);
}
/* There are 4 registers in the CRC custom instruction. Since
* this example uses CRC-32 only the first register must be read
* in order to receive the full result.
*/
return CRC_CI_MACRO(4, 0);
}

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ip/nios2_hw_crc/HAL/src/crc.c
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/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* Altera does not recommend, suggest or require that this reference design *
* file be used in conjunction or combination with any other product. *
******************************************************************************/
/**********************************************************************
*
* Filename: crc.c
*
* Description: Slow and fast implementations of the CRC standards.
*
* Notes: The parameters for each supported CRC standard are
* defined in the header file crc.h. The implementations
* here should stand up to further additions to that list.
*
*
* Copyright (c) 2000 by Michael Barr. This software is placed into
* the public domain and may be used for any purpose. However, this
* notice must not be changed or removed and no warranty is either
* expressed or implied by its publication or distribution.
**********************************************************************/
#include "crc.h"
/*
* Derive parameters from the standard-specific parameters in crc.h.
*/
#define WIDTH (8 * sizeof(crc))
#define TOPBIT (1 << (WIDTH - 1))
#if (REFLECT_DATA == TRUE)
#undef REFLECT_DATA
#define REFLECT_DATA(X) ((unsigned char) reflect((X), 8))
#else
#undef REFLECT_DATA
#define REFLECT_DATA(X) (X)
#endif
#if (REFLECT_REMAINDER == TRUE)
#undef REFLECT_REMAINDER
#define REFLECT_REMAINDER(X) ((crc) reflect((X), WIDTH))
#else
#undef REFLECT_REMAINDER
#define REFLECT_REMAINDER(X) (X)
#endif
/*********************************************************************
*
* Function: reflect()
*
* Description: Reorder the bits of a binary sequence, by reflecting
* them about the middle position.
*
* Notes: No checking is done that nBits <= 32.
*
* Returns: The reflection of the original data.
*
*********************************************************************/
static unsigned long
reflect(unsigned long data, unsigned char nBits)
{
unsigned long reflection = 0x00000000;
unsigned char bit;
/*
* Reflect the data about the center bit.
*/
for (bit = 0; bit < nBits; ++bit)
{
/*
* If the LSB bit is set, set the reflection of it.
*/
if (data & 0x01)
{
reflection |= (1 << ((nBits - 1) - bit));
}
data = (data >> 1);
}
return (reflection);
} /* reflect() */
/*********************************************************************
*
* Function: crcSlow()
*
* Description: Compute the CRC of a given message.
*
* Notes:
*
* Returns: The CRC of the message.
*
*********************************************************************/
crc
crcSlow(unsigned char const message[], int nBytes)
{
crc remainder = INITIAL_REMAINDER;
int byte;
unsigned char bit;
/*
* Perform modulo-2 division, a byte at a time.
*/
for (byte = 0; byte < nBytes; ++byte)
{
/*
* Bring the next byte into the remainder.
*/
remainder ^= (REFLECT_DATA(message[byte]) << (WIDTH - 8));
/*
* Perform modulo-2 division, a bit at a time.
*/
for (bit = 8; bit > 0; --bit)
{
/*
* Try to divide the current data bit.
*/
if (remainder & TOPBIT)
{
remainder = (remainder << 1) ^ POLYNOMIAL;
}
else
{
remainder = (remainder << 1);
}
}
}
/*
* The final remainder is the CRC result.
*/
return (REFLECT_REMAINDER(remainder) ^ FINAL_XOR_VALUE);
} /* crcSlow() */
crc crcTable[256];
/*********************************************************************
*
* Function: crcInit()
*
* Description: Populate the partial CRC lookup table.
*
* Notes: This function must be rerun any time the CRC standard
* is changed. If desired, it can be run "offline" and
* the table results stored in an embedded system's ROM.
*
* Returns: None defined.
*
*********************************************************************/
void
crcInit(void)
{
crc remainder;
int dividend;
unsigned char bit;
/*
* Compute the remainder of each possible dividend.
*/
for (dividend = 0; dividend < 256; ++dividend)
{
/*
* Start with the dividend followed by zeros.
*/
remainder = dividend << (WIDTH - 8);
/*
* Perform modulo-2 division, a bit at a time.
*/
for (bit = 8; bit > 0; --bit)
{
/*
* Try to divide the current data bit.
*/
if (remainder & TOPBIT)
{
remainder = (remainder << 1) ^ POLYNOMIAL;
}
else
{
remainder = (remainder << 1);
}
}
/*
* Store the result into the table.
*/
crcTable[dividend] = remainder;
}
} /* crcInit() */
/*********************************************************************
*
* Function: crcFast()
*
* Description: Compute the CRC of a given message.
*
* Notes: crcInit() must be called first.
*
* Returns: The CRC of the message.
*
*********************************************************************/
crc
crcFast(unsigned char const message[], int nBytes)
{
crc remainder = INITIAL_REMAINDER;
unsigned char data;
int byte;
/*
* Divide the message by the polynomial, a byte at a time.
*/
for (byte = 0; byte < nBytes; ++byte)
{
data = REFLECT_DATA(message[byte]) ^ (remainder >> (WIDTH - 8));
remainder = crcTable[data] ^ (remainder << 8);
}
/*
* The final remainder is the CRC.
*/
return (REFLECT_REMAINDER(remainder) ^ FINAL_XOR_VALUE);
} /* crcFast() */

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ip/nios2_hw_crc/hdl/CRC_Component.v
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/*
Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
This component supports 8, 16, 24, and 32 bit little endian data
and any CRC standard between 1 to 128 bits. Through parameterization
you can change the CRC standard which will take effect after you
regenerate your system in SOPC Builder.
Register Map:
000 -> reset the CRC peripheral to the inital value (data and byte enables ignored)
001 -> data write between 1-32 bits
010 -> reserved
011 -> reserved
100 -> read bits 1-32 of the crc result
101 -> read bits 33-64 of the crc result (where applicable)
110 -> read bits 65-96 of the crc result (where applicable)
111 -> read bits 97-128 of the crc result (where applicable)
Write latency = 0
Read latency = 1
Note: This component uses four blocks of eight bits of data in cascade.
To improve the timing of logic you can create seperate cascades
for 8, 16, 24, and 32 bit data which will allow for smaller area
and a shorter combinational depth. Since CRC logic consumes power
even when not in use you can also add a logic disable feature using
the chipselect signal. Even though the registered CRC value is
held constant when the circuit is not in use the input data will
change during this time and cause the CRC cascade logic to react.
*/
module CRC_Component (clk,
reset,
address,
writedata,
byteenable,
write,
read,
chipselect,
readdata);
/*
Using these parameters you can create any CRC ranging from one bit (parity checker)
up to 128 bits. The following list describes the function of each parameter:
crc_width:
The width of the registered CRC result, this value is typically apart of
the name of the standard (CRC32 is 32 bits wide). Adjusting this value
will impact the logic resource usage.
polynomial_initial:
The initial value set for the CRC result register. By writing any data to address 0
this value will be stored in the result register thereby clearing any previously existing
value. This value must be the same width as 'crc_width'
polynomial:
This is the divisor value used on the input data. Typically shown in polynomial format
the value symbolizes the placement of xor operation on the input data. In synthesis, the
polynomial bits that are '1' will create a not gate, whereas the bits that are '0' will
simply create a wire. Even with 32 stages of these operations cascaded, the simple logic
will not become a significant factor on logic utilization or fmax. This value must be the
same width as 'crc_width'
reflected_input:
Some CRC standards require that all the input bits be reflected around the center point.
This option is enabled with '1' and disabled with '0'. Typically this option is enabled
or disabled with 'reflected_output'.
reflected_output:
Some CRC standards require that all the output bits be reflected around the center point.
This operation occurs before the final optional xor output step. This option is enabled
with '1' and disabled with '0'. Typically this option is enabled or disabled with
'reflected_input' (to undo the input reversal typically).
xor_output:
This is the value used to bitwise xor the CRC result. Most standards use either all zeros
or all ones for this value. When zeros are used the CRC result is passed directly and when
ones are used the CRC result is inverted. Since it's no mandatory that this value be all
ones or zeros, this operation occurs before the output reflection when applicable.
*/
parameter crc_width = 32;
parameter polynomial_inital = 32'hFFFFFFFF;
parameter polynomial = 32'h04C11DB7;
parameter reflected_input = 1;
parameter reflected_output = 1;
parameter xor_output = 32'hFFFFFFFF;
input clk;
input reset;
input [2:0] address;
input [31:0] writedata;
input [3:0] byteenable;
input write;
input read;
input chipselect;
output [31:0] readdata;
reg [crc_width-1:0] crc_value;
wire [crc_width-1:0] poly = polynomial;
wire [crc_width-1:0] cascade [3:0];
wire [7:0] block0_data, block1_data, block2_data, block3_data;
wire [crc_width-1:0] result, result_xored;
wire [31:0] mux_result;
reg [31:0] readdata;
/*
Some standards like CRC16 and CRC32 require this bitreversal for serial
devices like ethernet, uarts, usb, etc...
*/
genvar index;
generate if (reflected_input == 1)
begin
for(index = 0; index < 8; index = index + 1)
begin: input_reflection
assign block0_data[index] = writedata[7-index];
assign block1_data[index] = writedata[15-index];
assign block2_data[index] = writedata[23-index];
assign block3_data[index] = writedata[31-index];
end
end
else
begin
assign block0_data = writedata[7:0];
assign block1_data = writedata[15:8];
assign block2_data = writedata[23:16];
assign block3_data = writedata[31:24];
end
endgenerate
/*
Control for the registered events. It assumes that either 8, 16, 24, or 32
bit data is being written using byte enables. It is important that the data
be in little endian format and no gaps of byte enables be present (like
1011 or 1101 for example)
*/
always @ (posedge clk or posedge reset)
begin
if(reset == 1)
begin
crc_value <= 0;
end
else
begin
if(write && chipselect && (address == 3'b000))
begin
crc_value <= polynomial_inital; // reset the crc to the initial value
end
else if(write && chipselect && (address == 3'b001))
begin
if(byteenable == 4'b0001) // 8 bit data input
begin
crc_value <= cascade[0];
end
else if(byteenable == 4'b0011) // 16 bit data input
begin
crc_value <= cascade[1];
end
else if(byteenable == 4'b0111) // 24 bit data input
begin
crc_value <= cascade[2];
end
else if(byteenable == 4'b1111) // 32 bit data input
begin
crc_value <= cascade[3];
end
end
end
end
/* four stages of cascade blocks (each block is crc_width x 8 bits) */
XOR_Shift_Block cascade_block0(.block_input(crc_value), .poly(poly), .data_input(block0_data), .block_output(cascade[0]));
defparam cascade_block0.crc_width = crc_width;
XOR_Shift_Block cascade_block1(.block_input(cascade[0]), .poly(poly), .data_input(block1_data), .block_output(cascade[1]));
defparam cascade_block1.crc_width = crc_width;
XOR_Shift_Block cascade_block2(.block_input(cascade[1]), .poly(poly), .data_input(block2_data), .block_output(cascade[2]));
defparam cascade_block2.crc_width = crc_width;
XOR_Shift_Block cascade_block3(.block_input(cascade[2]), .poly(poly), .data_input(block3_data), .block_output(cascade[3]));
defparam cascade_block3.crc_width = crc_width;
/*
Some standards like CRC16 and CRC32 require this bitreversal.
This is to better support serial devices like uarts, ethernet, usb, etc...)
*/
generate if (reflected_output == 1)
begin
for(index = 0; index < crc_width; index = index + 1)
begin: output_reflection32
assign result[index] = crc_value[(crc_width-1)-index];
end
end
else
begin
assign result = crc_value;
end
endgenerate
/* This final xor operation occurs after the bit swap */
assign result_xored = result ^ xor_output;
/* Generates the appropriate MUX logic depending on the CRC width */
generate if((crc_width > 32) && (crc_width < 65))
begin
assign mux_result = (address == 3'b100)? result_xored[31:0] : result_xored[crc_width-1:32];
end
else if((crc_width > 64) && (crc_width < 97))
begin
assign mux_result = (address == 3'b100)? result_xored[31:0] :
((address == 3'b101)? result_xored[63:32] : result_xored[crc_width-1:64]);
end
else if((crc_width > 96) && (crc_width < 129))
begin
assign mux_result = (address == 3'b100)? result_xored[31:0] :
((address == 3'b101)? result_xored[63:32] :
((address == 3'b110)? result_xored[95:64] : result_xored[crc_width-1:96]));
end
else
begin
assign mux_result = result_xored;
end
endgenerate
/* Registering the return path of the CRC data (32 bits of it) */
always @ (posedge clk or posedge reset)
begin
if(reset == 1)
begin
readdata <= 0;
end
else if((read == 1) && (chipselect == 1))
begin
readdata <= mux_result;
end
end
endmodule
/* a single cascade block of width: crc_width and a length of eight input bits */
module XOR_Shift_Block(block_input,
poly,
data_input,
block_output);
parameter crc_width = 32;
input [(crc_width-1):0] block_input;
input [(crc_width-1):0] poly;
input [7:0] data_input;
output [(crc_width-1):0] block_output;
wire [(crc_width-1):0] cascade [7:0];
XOR_Shift bit_0(.stage_input(block_input), .poly(poly), .new_bit(data_input[7]), .stage_output(cascade[0]));
defparam bit_0.crc_width = crc_width;
XOR_Shift bit_1(.stage_input(cascade[0]), .poly(poly), .new_bit(data_input[6]), .stage_output(cascade[1]));
defparam bit_1.crc_width = crc_width;
XOR_Shift bit_2(.stage_input(cascade[1]), .poly(poly), .new_bit(data_input[5]), .stage_output(cascade[2]));
defparam bit_2.crc_width = crc_width;
XOR_Shift bit_3(.stage_input(cascade[2]), .poly(poly), .new_bit(data_input[4]), .stage_output(cascade[3]));
defparam bit_3.crc_width = crc_width;
XOR_Shift bit_4(.stage_input(cascade[3]), .poly(poly), .new_bit(data_input[3]), .stage_output(cascade[4]));
defparam bit_4.crc_width = crc_width;
XOR_Shift bit_5(.stage_input(cascade[4]), .poly(poly), .new_bit(data_input[2]), .stage_output(cascade[5]));
defparam bit_5.crc_width = crc_width;
XOR_Shift bit_6(.stage_input(cascade[5]), .poly(poly), .new_bit(data_input[1]), .stage_output(cascade[6]));
defparam bit_6.crc_width = crc_width;
XOR_Shift bit_7(.stage_input(cascade[6]), .poly(poly), .new_bit(data_input[0]), .stage_output(cascade[7]));
defparam bit_7.crc_width = crc_width;
assign block_output = cascade[7];
endmodule
/* performs the 'new_bit' stuffing, shifting, and XOR operations for a single input bit */
module XOR_Shift (stage_input,
poly,
new_bit,
stage_output);
parameter crc_width = 32;
input [crc_width-1:0] stage_input;
input [crc_width-1:0] poly;
input new_bit;
output [crc_width-1:0] stage_output;
assign stage_output[0] = new_bit ^ stage_input[crc_width-1];
assign stage_output[crc_width-1:1] = stage_input[crc_width-2:0] ^ ({crc_width-1{stage_output[0]}} & poly[crc_width-1:1]);
endmodule

101
ip/nios2_hw_crc/hdl/CRC_Custom_Instruction.v
View File

@ -1,101 +0,0 @@
/*
Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
This thin wrapper re-uses the CRC Avalon component as a Nios II
custom instruction. The n port of custom instruction is used as
control to the CRC Avalon component. Below are the values of n and
the corresponding operations perform by the custom instruction:
n = 0, Initialize the custom instruction to the initial remainder value
n = 1, Write 8 bits data to custom instruction
n = 2, Write 16 bits data to custom instruction
n = 3, Write 32 bits data to custom instruction
n = 4, Read 32 bits data from the custom instruction
n = 5, Read 64 bits data from the custom instruction
n = 6, Read 96 bits data from the custom instruction
n = 7, Read 128 bits data from the custom instruction
*/
module CRC_Custom_Instruction(clk,
reset,
dataa,
n,
clk_en,
start,
done,
result);
/*
See the Avalon CRC component for details on the meaning of each
parameter listed below.
*/
parameter crc_width = 32;
parameter polynomial_inital = 32'hFFFFFFFF;
parameter polynomial = 32'h04C11DB7;
parameter reflected_input = 1;
parameter reflected_output = 1;
parameter xor_output = 32'hFFFFFFFF;
input clk;
input reset;
input [31:0] dataa;
input [2:0] n;
input clk_en;
input start;
output done;
output [31:0] result;
wire [2:0] address;
wire [3:0] byteenable;
wire write;
wire read;
reg done_delay;
assign write = (n<4);
assign read = (n>3);
assign byteenable = (n==1)?4'b0001 : (n==2)?4'b0011 : (n==3)?4'b1111 : 4'b0000;
assign address = (n==0)?3'b000 : ((n==1)|(n==2)|(n==3))?3'b001 : (n==4)?3'b100 : (n==5)?3'b101 : (n==6)?3'b110 : 3'b111;
assign done = (n>3)? done_delay : start;
always @ (posedge clk or posedge reset)
begin
if (reset)
done_delay <= 0;
else
done_delay <= start;
end
/*
Instantiating the Avalon CRC component and wiring it to be
custom instruction compilant
*/
CRC_Component wrapper_wiring(.clk(clk),
.reset(reset),
.address(address),
.writedata(dataa),
.byteenable(byteenable),
.write(write & start),
.read(read),
.chipselect(clk_en),
.readdata(result));
defparam wrapper_wiring.crc_width = crc_width;
defparam wrapper_wiring.polynomial_inital = polynomial_inital;
defparam wrapper_wiring.polynomial = polynomial;
defparam wrapper_wiring.reflected_input = reflected_input;
defparam wrapper_wiring.reflected_output = reflected_output;
defparam wrapper_wiring.xor_output = xor_output;
endmodule

116
ip/nios2_hw_crc/nios2_hw_crc32_hw.tcl
View File

@ -1,116 +0,0 @@
# TCL File Generated by Component Editor 15.1
# Tue Dec 22 18:46:40 EET 2015
# DO NOT MODIFY
#
# nios2_hw_crc32 "nios2_hw_crc32" v1.0
# 2015.12.22.18:46:40
#
#
#
# request TCL package from ACDS 15.1
#
package require -exact qsys 15.1
#
# module nios2_hw_crc32
#
set_module_property DESCRIPTION ""
set_module_property NAME nios2_hw_crc32
set_module_property VERSION 17.1
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP "Custom Instruction Modules"
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME nios2_hw_crc32
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL CRC_Custom_Instruction
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file CRC_Component.v VERILOG PATH hdl/CRC_Component.v
add_fileset_file CRC_Custom_Instruction.v VERILOG PATH hdl/CRC_Custom_Instruction.v TOP_LEVEL_FILE
#
# parameters
#
add_parameter crc_width INTEGER 32
set_parameter_property crc_width DEFAULT_VALUE 32
set_parameter_property crc_width DISPLAY_NAME crc_width
set_parameter_property crc_width TYPE INTEGER
set_parameter_property crc_width UNITS None
set_parameter_property crc_width HDL_PARAMETER true
add_parameter polynomial_inital STD_LOGIC_VECTOR 4294967295
set_parameter_property polynomial_inital DEFAULT_VALUE 4294967295
set_parameter_property polynomial_inital DISPLAY_NAME polynomial_inital
set_parameter_property polynomial_inital TYPE STD_LOGIC_VECTOR
set_parameter_property polynomial_inital UNITS None
set_parameter_property polynomial_inital ALLOWED_RANGES 0:17179869183
set_parameter_property polynomial_inital HDL_PARAMETER true
add_parameter polynomial STD_LOGIC_VECTOR 79764919
set_parameter_property polynomial DEFAULT_VALUE 79764919
set_parameter_property polynomial DISPLAY_NAME polynomial
set_parameter_property polynomial TYPE STD_LOGIC_VECTOR
set_parameter_property polynomial UNITS None
set_parameter_property polynomial ALLOWED_RANGES 0:17179869183
set_parameter_property polynomial HDL_PARAMETER true
add_parameter reflected_input INTEGER 1
set_parameter_property reflected_input DEFAULT_VALUE 1
set_parameter_property reflected_input DISPLAY_NAME reflected_input
set_parameter_property reflected_input TYPE INTEGER
set_parameter_property reflected_input UNITS None
set_parameter_property reflected_input HDL_PARAMETER true
add_parameter reflected_output INTEGER 1
set_parameter_property reflected_output DEFAULT_VALUE 1
set_parameter_property reflected_output DISPLAY_NAME reflected_output
set_parameter_property reflected_output TYPE INTEGER
set_parameter_property reflected_output UNITS None
set_parameter_property reflected_output HDL_PARAMETER true
add_parameter xor_output STD_LOGIC_VECTOR 4294967295
set_parameter_property xor_output DEFAULT_VALUE 4294967295
set_parameter_property xor_output DISPLAY_NAME xor_output
set_parameter_property xor_output TYPE STD_LOGIC_VECTOR
set_parameter_property xor_output UNITS None
set_parameter_property xor_output ALLOWED_RANGES 0:17179869183
set_parameter_property xor_output HDL_PARAMETER true
#
# display items
#
#
# connection point nios_custom_instruction_slave
#
add_interface nios_custom_instruction_slave nios_custom_instruction end
set_interface_property nios_custom_instruction_slave clockCycle 0
set_interface_property nios_custom_instruction_slave operands 1
set_interface_property nios_custom_instruction_slave ENABLED true
set_interface_property nios_custom_instruction_slave EXPORT_OF ""
set_interface_property nios_custom_instruction_slave PORT_NAME_MAP ""
set_interface_property nios_custom_instruction_slave CMSIS_SVD_VARIABLES ""
set_interface_property nios_custom_instruction_slave SVD_ADDRESS_GROUP ""
add_interface_port nios_custom_instruction_slave clk clk Input 1
add_interface_port nios_custom_instruction_slave clk_en clk_en Input 1
add_interface_port nios_custom_instruction_slave dataa dataa Input 32
add_interface_port nios_custom_instruction_slave done done Output 1
add_interface_port nios_custom_instruction_slave n n Input 3
add_interface_port nios_custom_instruction_slave reset reset Input 1
add_interface_port nios_custom_instruction_slave result result Output 32
add_interface_port nios_custom_instruction_slave start start Input 1

58
ip/nios2_hw_crc/nios2_hw_crc32_sw.tcl
View File

@ -1,58 +0,0 @@
# (C) 2001-2015 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and other
# software and tools, and its AMPP partner logic functions, and any output
# files any of the foregoing (including device programming or simulation
# files), and any associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License Subscription
# Agreement, Altera MegaCore Function License Agreement, or other applicable
# license agreement, including, without limitation, that your use is for the
# sole purpose of programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the applicable
# agreement for further details.
# TCL File Generated by Altera University Program
# DO NOT MODIFY
set aup_version 15.1
# Create a new driver - this name must be different than the
# hardware component name
create_driver nios2_hw_crc32_driver
# Associate it with some hardware
set_sw_property hw_class_name nios2_hw_crc32
# The version of this driver
set_sw_property version $aup_version
# This driver is proclaimed to be compatible with 'component'
# as old as version "1.0". The component hardware version is set in the
# _hw.tcl file - If the hardware component version number is not equal
# or greater than the min_compatable_hw_version number, the driver
# source files will not be copied over to the BSP driver directory
set_sw_property min_compatible_hw_version 1.0
# Initialize the driver in alt_sys_init()
set_sw_property auto_initialize false
# Location in generated BSP that sources will be copied into
set_sw_property bsp_subdirectory drivers
#
# Source file listings...
#
# C/C++ source files
add_sw_property c_source HAL/src/ci_crc.c
add_sw_property c_source HAL/src/crc.c
# Include files
add_sw_property include_source HAL/inc/ci_crc.h
add_sw_property include_source HAL/inc/crc.h
# This driver supports HAL type
add_sw_property supported_bsp_type HAL
# End of file

1
ip/pulpino_qsys Submodule

@ -0,0 +1 @@
Subproject commit b11dd7718e6d367cbaef8a362ce206510fd87ed0

8
rtl/ossc.v
View File

@ -83,6 +83,7 @@ wire DE_out_videogen;
reg [7:0] cpu_reset_ctr = 0;
reg cpu_reset_n = 1'b0;
wire ext_reset_req;
reg [7:0] R_in_L, G_in_L, B_in_L;
reg HSYNC_in_L, VSYNC_in_L, FID_in_L;
@ -226,7 +227,12 @@ end
sys sys_inst(
.clk_clk (clk27),
.reset_reset_n (cpu_reset_n),
.reset_reset_n (cpu_reset_n & ~ext_reset_req),
.pulpino_0_config_testmode_i (1'b0),
.pulpino_0_config_fetch_enable_i (1'b1),
.pulpino_0_config_clock_gating_i (1'b0),
.pulpino_0_config_boot_addr_i (32'h00010000),
.master_0_master_reset_reset (ext_reset_req),
.i2c_opencores_0_export_scl_pad_io (scl),
.i2c_opencores_0_export_sda_pad_io (sda),
.i2c_opencores_0_export_spi_miso_pad_i (1'b0),

25
scripts/rv-reprogram.tcl Normal file
View File

@ -0,0 +1,25 @@
#Select the master service type and check for available service paths.
set service_paths [get_service_paths master]
#Set the master service path.
set master_service_path [lindex $service_paths 0]
#Open the master service.
set claim_path [claim_service master $master_service_path mylib]
puts "Halting CPU"
master_write_32 $claim_path 0x0 0x1
puts "Writing block RAM"
master_write_from_file $claim_path mem_init/sys_onchip_memory2_0.bin 0x10000
close_service master $claim_path
set jtag_debug_list [get_service_paths jtag_debug]
set jd [ lindex $jtag_debug_list 0 ]
open_service jtag_debug $jd
puts "Resetting system"
jtag_debug_reset_system $jd
close_service jtag_debug $jd
puts "Done"

2
software/ossc_sw.project
View File

@ -161,7 +161,7 @@
</Compiler>
<Linker Options="-O2" Required="yes"/>
<ResourceCompiler Options="" Required="no"/>
<General OutputFile="" IntermediateDirectory="./Release" Command="nios2-download -g --accept-bad-sysid sys_controller.elf" CommandArguments="" UseSeparateDebugArgs="no" DebugArguments="" WorkingDirectory="$(ProjectPath)/sys_controller" PauseExecWhenProcTerminates="no" IsGUIProgram="no" IsEnabled="yes"/>
<General OutputFile="" IntermediateDirectory="./Release" Command="make rv-reprogram" CommandArguments="" UseSeparateDebugArgs="no" DebugArguments="" WorkingDirectory="$(ProjectPath)/sys_controller" PauseExecWhenProcTerminates="no" IsGUIProgram="no" IsEnabled="yes"/>
<BuildSystem Name="Default"/>
<Environment EnvVarSetName="&lt;Use Defaults&gt;" DbgSetName="&lt;Use Defaults&gt;">
<![CDATA[]]>

15
software/sys_controller/Makefile
View File

@ -754,6 +754,8 @@ ifeq ($(MKDIR),)
MKDIR := $(DEFAULT_MKDIR)
endif
RV_OBJCOPY = riscv64-unknown-elf-objcopy
#------------------------------------------------------------------------------
# PATTERN RULES TO BUILD OBJECTS
#------------------------------------------------------------------------------
@ -1127,5 +1129,16 @@ print-elf-name:
ossc/menu_sjis.c: ossc/menu.c
iconv -f UTF-8 -t SHIFT-JIS ossc/menu.c > ossc/menu_sjis.c
mem_init/sys_onchip_memory2_0.hex: sys_controller.elf
$(RV_OBJCOPY) --change-addresses -0x10000 -O binary --gap-fill 0 $< mem_init/sys_onchip_memory2_0.bin
../../tools/bin2hex mem_init/sys_onchip_memory2_0.bin mem_init/sys_onchip_memory2_0.hex
.PHONY: mem_init_generate_new
mem_init_generate_new: mem_init/sys_onchip_memory2_0.hex
.PHONY: generate_hex
generate_hex: clean mem_init_generate
generate_hex: clean mem_init_generate_new
.PHONY: rv-reprogram
rv-reprogram: mem_init_generate_new
system-console -cli --script ../../scripts/rv-reprogram.tcl

103
software/sys_controller/crt0.boot.S Normal file
View File

@ -0,0 +1,103 @@
// Copyright 2017 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the “License”); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
#include "pulpino.h"
#define EXCEPTION_STACK_SIZE 72
/* ========================================================= [ entry ] === */
.section .text
default_exc_handler:
jal x0, default_exc_handler
reset_handler:
/* set all registers to zero */
mv x1, x0
mv x2, x1
mv x3, x1
mv x4, x1
mv x5, x1
mv x6, x1
mv x7, x1
mv x8, x1
mv x9, x1
mv x10, x1
mv x11, x1
mv x12, x1
mv x13, x1
mv x14, x1
mv x15, x1
mv x16, x1
mv x17, x1
mv x18, x1
mv x19, x1
mv x20, x1
mv x21, x1
mv x22, x1
mv x23, x1
mv x24, x1
mv x25, x1
mv x26, x1
mv x27, x1
mv x28, x1
mv x29, x1
mv x30, x1
mv x31, x1
/* stack initilization */
la x2, _stack_start
_start:
.global _start
/* clear BSS */
la x26, _bss_start
la x27, _bss_end
bge x26, x27, zero_loop_end
zero_loop:
sw x0, 0(x26)
addi x26, x26, 4
ble x26, x27, zero_loop
zero_loop_end:
main_entry:
/* jump to alt_main program entry point */
jal alt_main
/* =================================================== [ exceptions ] === */
/* This section has to be down here, since we have to disable rvc for it */
.section .vectors, "ax"
.option norvc;
// external interrupts are handled by the same callback
// until compiler supports IRQ routines
.org 0x00
.rept 31
nop
.endr
jal x0, default_exc_handler
// reset vector
.org 0x80
jal x0, reset_handler
// illegal instruction exception
.org 0x84
jal x0, default_exc_handler
// ecall handler
.org 0x88
jal x0, default_exc_handler

2
software/sys_controller/it6613/hdmitx.h
View File

@ -52,7 +52,7 @@
//#define NULL 0
//typedef unsigned char bool;
#include "Altera_UP_SD_Card_Avalon_Interface_mod.h"
typedef unsigned char bool;
#include "sysconfig.h"
// Hardwired to CPU reset

135
software/sys_controller/link.common.ld Normal file
View File

@ -0,0 +1,135 @@
SEARCH_DIR(.)
__DYNAMIC = 0;
MEMORY
{
dataram : ORIGIN = 0x00010000, LENGTH = 0x9000
}
/* Stack information variables */
_min_stack = 0x400; /* 1K - minimum stack space to reserve */
_stack_start = ORIGIN(dataram) + LENGTH(dataram);
/* We have to align each sector to word boundaries as our current s19->slm
* conversion scripts are not able to handle non-word aligned sections. */
SECTIONS
{
.vectors :
{
. = ALIGN(4);
KEEP(*(.vectors))
} > dataram
.text : {
. = ALIGN(4);
_stext = .;
*(.text)
*(.text.*)
_etext = .;
__CTOR_LIST__ = .;
LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
*(.ctors)
LONG(0)
__CTOR_END__ = .;
__DTOR_LIST__ = .;
LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
*(.dtors)
LONG(0)
__DTOR_END__ = .;
*(.lit)
*(.shdata)
_endtext = .;
} > dataram
/*--------------------------------------------------------------------*/
/* Global constructor/destructor segement */
/*--------------------------------------------------------------------*/
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
} > dataram
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array ))
PROVIDE_HIDDEN (__init_array_end = .);
} > dataram
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array ))
PROVIDE_HIDDEN (__fini_array_end = .);
} > dataram
.rodata : {
. = ALIGN(4);
*(.rodata);
*(.rodata.*)
} > dataram
.shbss :
{
. = ALIGN(4);
*(.shbss)
} > dataram
.data : {
. = ALIGN(4);
sdata = .;
_sdata = .;
*(.data);
*(.data.*)
*(.sdata);
*(.sdata.*)
*(.sdata2);
*(.sdata2.*)
edata = .;
_edata = .;
} > dataram
.bss :
{
. = ALIGN(4);
_bss_start = .;
*(.bss)
*(.bss.*)
*(.sbss)
*(.sbss.*)
*(COMMON)
_bss_end = .;
} > dataram
/* ensure there is enough room for stack */
.stack (NOLOAD): {
. = ALIGN(4);
. = . + _min_stack ;
. = ALIGN(4);
stack = . ;
_stack = . ;
} > dataram
.stab 0 (NOLOAD) :
{
[ .stab ]
}
.stabstr 0 (NOLOAD) :
{
[ .stabstr ]
}
.bss :
{
. = ALIGN(4);
_end = .;
} > dataram
}

7
software/sys_controller/link.riscv.ld Normal file
View File

@ -0,0 +1,7 @@
/* not needed, but we need separate linker scripts anyway */
OUTPUT_ARCH(riscv)
/* required to correctly link newlib */
GROUP( -lc -lgloss -lgcc -lsupc++ )
INCLUDE link.common.ld

8646
software/sys_controller/mem_init/sys_onchip_memory2_0.hex
View File

File diff suppressed because it is too large Load Diff

2
software/sys_controller/ossc/controls.c
View File

@ -163,7 +163,7 @@ int parse_control()
((fpga_status >> 16) & 0x3) ? '*' : ' ',
fpga_v_hz_x100/100,
fpga_v_hz_x100%100);*/
sniprintf(menu_row2, LCD_ROW_LEN+1, "%4lu%c%c %u", (((fpga_status & 0x7ff)+1)<<fpga_ilace)+fpga_ilace,
sniprintf(menu_row2, LCD_ROW_LEN+1, "%4lu%c%c %lu", (((fpga_status & 0x7ff)+1)<<fpga_ilace)+fpga_ilace,
fpga_ilace ? 'i' : 'p',
((fpga_status >> 16) & 0x3) ? '*' : ' ',
IORD_ALTERA_AVALON_PIO_DATA(PIO_8_BASE));

2
software/sys_controller/ossc/firmware.h
View File

@ -24,7 +24,7 @@
#include "sysconfig.h"
#define FW_VER_MAJOR 0
#define FW_VER_MINOR 81
#define FW_VER_MINOR 82
#ifdef ENABLE_AUDIO
#define FW_SUFFIX1 "a"

91
software/sys_controller/pulpino.h Normal file
View File

@ -0,0 +1,91 @@
// Copyright 2017 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the “License”); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
/**
* @file
* @brief Register mapping for PULPino peripherals.
*
* Contains event register mappings for the PULPino SOC as
* well as some general definitions for the overall system.
*
* @author Florian Zaruba
*
* @version 1.0
*
* @date 2/10/2015
*
*/
#ifndef PULPINO_H
#define PULPINO_H
#define PULPINO_BASE_ADDR 0x10000000
/** SOC PERIPHERALS */
#define SOC_PERIPHERALS_BASE_ADDR ( PULPINO_BASE_ADDR + 0xA100000 )
#define UART_BASE_ADDR ( SOC_PERIPHERALS_BASE_ADDR + 0x0000 )
#define GPIO_BASE_ADDR ( SOC_PERIPHERALS_BASE_ADDR + 0x1000 )
#define SPI_BASE_ADDR ( SOC_PERIPHERALS_BASE_ADDR + 0x2000 )
#define TIMER_BASE_ADDR ( SOC_PERIPHERALS_BASE_ADDR + 0x3000 )
#define EVENT_UNIT_BASE_ADDR ( SOC_PERIPHERALS_BASE_ADDR + 0x4000 )
#define I2C_BASE_ADDR ( SOC_PERIPHERALS_BASE_ADDR + 0x5000 )
#define FLL_BASE_ADDR ( SOC_PERIPHERALS_BASE_ADDR + 0x6000 )
#define SOC_CTRL_BASE_ADDR ( SOC_PERIPHERALS_BASE_ADDR + 0x7000 )
/** STDOUT */
#define STDOUT_BASE_ADDR ( SOC_PERIPHERALS_BASE_ADDR + 0x10000 )
#define FPUTCHAR_BASE_ADDR ( STDOUT_BASE_ADDR + 0x1000 )
#define FILE_CMD_BASE_ADDR ( STDOUT_BASE_ADDR + 0x2000 )
#define STREAM_BASE_ADDR ( STDOUT_BASE_ADDR + 0x3000 )
/** Instruction RAM */
#define INSTR_RAM_BASE_ADDR ( 0x00 )
#define INSTR_RAM_START_ADDR ( 0x80 )
/** ROM */
#define ROM_BASE_ADDR ( 0x10000 )
/** Data RAM */
#define DATA_RAM_BASE_ADDR ( 0x00100000 )
/** Registers and pointers */
#define REGP(x) ((volatile unsigned int*)(x))
#define REG(x) (*((volatile unsigned int*)(x)))
#define REGP_8(x) (((volatile uint8_t*)(x)))
/* pointer to mem of apb pulpino unit - PointerSocCtrl */
#define __PSC__(a) *(unsigned volatile int*) (SOC_CTRL_BASE_ADDR + a)
/** Peripheral Clock gating */
#define CGREG __PSC__(0x04)
/** Clock gate SPI */
#define CGSPI 0x00
/** Clock gate UART */
#define CGUART 0x01
/** Clock gate GPIO */
#define CGGPIO 0x02
/** Clock gate SPI Master */
#define CGGSPIM 0x03
/** Clock gate Timer */
#define CGTIM 0x04
/** Clock gate Event Unit */
#define CGEVENT 0x05
/** Clock gate I2C */
#define CGGI2C 0x06
/** Clock gate FLL */
#define CGFLL 0x07
/** Boot address register */
#define BOOTREG __PSC__(0x08)
#define RES_STATUS __PSC__(0x14)
#endif

74
software/sys_controller_bsp/HAL/src/alt_busy_sleep.c
View File

@ -57,77 +57,13 @@ unsigned int alt_busy_sleep (unsigned int us)
* skipped to speed up simulation.
*/
#ifndef ALT_SIM_OPTIMIZE
int i;
int big_loops;
alt_u32 cycles_per_loop;
if (!strcmp(NIOS2_CPU_IMPLEMENTATION,"tiny"))
{
cycles_per_loop = 9;
}
else
{
cycles_per_loop = 3;
}
unsigned long i, loops;
big_loops = us / (INT_MAX/
(ALT_CPU_FREQ/(cycles_per_loop * 1000000)));
// 1 loop >= 7 cyc
loops = ((ALT_CPU_FREQ/1000000)*us)/7;
if (big_loops)
{
for(i=0;i<big_loops;i++)
{
/*
* Do NOT Try to single step the asm statement below
* (single step will never return)
* Step out of this function or set a breakpoint after the asm statements
*/
__asm__ volatile (
"\n0:"
"\n\taddi %0,%0, -1"
"\n\tbne %0,zero,0b"
"\n1:"
"\n\t.pushsection .debug_alt_sim_info"
"\n\t.int 4, 0, 0b, 1b"
"\n\t.popsection"
:: "r" (INT_MAX));
us -= (INT_MAX/(ALT_CPU_FREQ/
(cycles_per_loop * 1000000)));
}
/*
* Do NOT Try to single step the asm statement below
* (single step will never return)
* Step out of this function or set a breakpoint after the asm statements
*/
__asm__ volatile (
"\n0:"
"\n\taddi %0,%0, -1"
"\n\tbne %0,zero,0b"
"\n1:"
"\n\t.pushsection .debug_alt_sim_info"
"\n\t.int 4, 0, 0b, 1b"
"\n\t.popsection"
:: "r" (us*(ALT_CPU_FREQ/(cycles_per_loop * 1000000))));
}
else
{
/*
* Do NOT Try to single step the asm statement below
* (single step will never return)
* Step out of this function or set a breakpoint after the asm statements
*/
__asm__ volatile (
"\n0:"
"\n\taddi %0,%0, -1"
"\n\tbgt %0,zero,0b"
"\n1:"
"\n\t.pushsection .debug_alt_sim_info"
"\n\t.int 4, 0, 0b, 1b"
"\n\t.popsection"
:: "r" (us*(ALT_CPU_FREQ/(cycles_per_loop * 1000000))));
}
for (i=7; i<loops; i++)
asm volatile ("nop");
#endif /* #ifndef ALT_SIM_OPTIMIZE */
return 0;
}

189
ip/nios2_hw_crc/HAL/inc/crc.h → software/sys_controller_bsp/HAL/src/alt_putcharbuf.c
View File

@ -1,109 +1,80 @@
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* Altera does not recommend, suggest or require that this reference design *
* file be used in conjunction or combination with any other product. *
******************************************************************************/
/**********************************************************************
*
* Filename: crc.h
*
* Description: A header file describing the various CRC standards.
*
* Notes:
*
*
* Copyright (c) 2000 by Michael Barr. This software is placed into
* the public domain and may be used for any purpose. However, this
* notice must not be changed or removed and no warranty is either
* expressed or implied by its publication or distribution.
**********************************************************************/
#ifndef _crc_h
#define _crc_h
#define FALSE 0
#define TRUE !FALSE
/*
* Select the CRC standard from the list that follows.
*/
#define CRC32
#if defined(CRC_CCITT)
typedef unsigned short crc;
#define CRC_NAME "CRC-CCITT"
#define POLYNOMIAL 0x1021
#define INITIAL_REMAINDER 0xFFFF
#define FINAL_XOR_VALUE 0x0000
#define REFLECT_DATA FALSE
#define REFLECT_REMAINDER FALSE
#define CHECK_VALUE 0x29B1
#elif defined(CRC16)
typedef unsigned short crc;
#define CRC_NAME "CRC-16"
#define POLYNOMIAL 0x8005
#define INITIAL_REMAINDER 0x0000
#define FINAL_XOR_VALUE 0x0000
#define REFLECT_DATA TRUE
#define REFLECT_REMAINDER TRUE
#define CHECK_VALUE 0xBB3D
#elif defined(CRC32)
typedef unsigned long crc;
#define CRC_NAME "CRC-32"
#define POLYNOMIAL 0x04C11DB7
#define INITIAL_REMAINDER 0xFFFFFFFF
#define FINAL_XOR_VALUE 0xFFFFFFFF
#define REFLECT_DATA TRUE
#define REFLECT_REMAINDER TRUE
#define CHECK_VALUE 0xCBF43926
#else
#error "One of CRC_CCITT, CRC16, or CRC32 must be #define'd."
#endif
void crcInit(void);
crc crcSlow(unsigned char const message[], int nBytes);
crc crcFast(unsigned char const message[], int nBytes);
#endif /* _crc_h */
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2015 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
* Altera does not recommend, suggest or require that this reference design *
* file be used in conjunction or combination with any other product. *
******************************************************************************/
#ifdef ALT_SEMIHOSTING
#include "sys/alt_stdio.h"
#include "unistd.h"
#ifndef ALT_PUTBUF_SIZE
#define ALT_PUTBUF_SIZE 64
#endif
// Buffer for the printed chars
static char buf[ALT_PUTBUF_SIZE] ={0};
// index into the buffer
static unsigned int fill_index;
/*
* ALT putcharbuf funtion
* Used only for semihosting.
* Not thread safe!
* This fucntion buffers up chars to be printed until either alt_putbufflush()
* is called or the buffer is full.
* It is called by alt_printf when semihosting is turned on
* Its purpose is to minimize the number of Break 1 issuesd by the semihosting
* libraries.
*/
int
alt_putcharbuf(int c)
{
buf[fill_index++] = (char)(c & 0xff);
if(fill_index >= ALT_PUTBUF_SIZE)
alt_putbufflush();
return c;
}
/*
* ALT putbufflush
* used only for smehosting
* Not thread safe!
* Dumps all the chars in the buffer to STDOUT
*/
int
alt_putbufflush()
{
int results;
results = write(STDOUT_FILENO,buf,fill_index);
fill_index = 0;
return results;
}
#endif

1
software/sys_controller_bsp/Makefile
View File

@ -256,6 +256,7 @@ hal_C_LIB_SRCS := \
$(hal_SRCS_ROOT)/src/alt_dev_llist_insert.c \
$(hal_SRCS_ROOT)/src/alt_errno.c \
$(hal_SRCS_ROOT)/src/alt_flash_dev.c \
$(hal_SRCS_ROOT)/src/alt_main.c
# i2c_opencores_driver sources root
i2c_opencores_driver_SRCS_ROOT := drivers

8
software/sys_controller_bsp/alt_sys_init.c
View File

@ -83,11 +83,11 @@ I2C_OPENCORES_INSTANCE ( I2C_OPENCORES_1, i2c_opencores_1);
* present for backwards-compatibility.
*/
/*void alt_irq_init ( const void* base )
void alt_irq_init ( const void* base )
{
ALTERA_NIOS2_GEN2_IRQ_INIT ( NIOS2_QSYS_0, nios2_qsys_0);
alt_irq_cpu_enable_interrupts();
}*/
/*ALTERA_NIOS2_GEN2_IRQ_INIT ( NIOS2_QSYS_0, nios2_qsys_0);
alt_irq_cpu_enable_interrupts();*/
}
/*
* Initialize the non-interrupt controller devices.

166
software/sys_controller_bsp/drivers/inc/Altera_UP_SD_Card_Avalon_Interface_mod.h
View File

@ -1,166 +0,0 @@
#ifndef __ALTERA_UP_SD_CARD_AVALON_INTERFACE_H__
#define __ALTERA_UP_SD_CARD_AVALON_INTERFACE_H__
#include <stddef.h>
#include <alt_types.h>
#include <sys/alt_dev.h>
#ifdef __cplusplus
extern "C"
{
#endif /* __cplusplus */
#define SD_RAW_IFACE
/*
* Device structure definition. Each instance of the driver uses one
* of these structures to hold its associated state.
*/
typedef struct alt_up_sd_card_dev {
/// @brief character mode device structure
/// @sa Developing Device Drivers for the HAL in Nios II Software Developer's Handbook
alt_dev dev;
/// @brief the base address of the device
unsigned int base;
} alt_up_sd_card_dev;
#ifndef bool
typedef enum e_bool { false = 0, true = 1 } bool;
#endif
//////////////////////////////////////////////////////////////////////////
// HAL system functions
alt_up_sd_card_dev* alt_up_sd_card_open_dev(const char *name);
/* Open an SD Card Interface if it is connected to the system. */
bool alt_up_sd_card_is_Present(void);
/* Check if there is an SD Card insterted into the SD Card socket.
*/
#ifndef SD_RAW_IFACE
bool alt_up_sd_card_is_FAT16(void);
/* This function reads the SD card data in an effort to determine if the card is formated as a FAT16
* volume. Please note that FAT12 has a similar format, but will not be supported by this driver.
*/
short int alt_up_sd_card_fopen(char *name, bool create);
/* This function reads the SD card data in an effort to determine if the card is formated as a FAT16
* volume. Please note that FAT12 has a similar format, but will not be supported by this driver.
*
* Inputs:
* name - a file name including a directory, relative to the root directory
* create - a flag set to true to create a file if it does not already exist
* Output:
* An index to the file record assigned to the specified file. -1 is returned if the file could not be opened.
*/
short int alt_up_sd_card_find_first(char *directory_to_search_through, char *file_name);
/* This function sets up a search algorithm to go through a given directory looking for files.
* If the search directory is valid, then the function searches for the first file it finds.
* Inputs:
* directory_to_search_through - name of the directory to search through
* file_name - an array to store a name of the file found. Must be 13 bytes long (12 bytes for file name and 1 byte of NULL termination).
* Outputs:
* 0 - success
* 1 - invalid directory
* 2 - No card or incorrect card format.
*
* To specify a directory give the name in a format consistent with the following regular expression:
* [{[valid_chars]+}/]*.
*
* In other words, give a path name starting at the root directory, where each directory name is followed by a '/'.
* Then, append a '.' to the directory name. Examples:
* "." - look through the root directory
* "first/." - look through a directory named "first" that is located in the root directory.
* "first/sub/." - look through a directory named "sub", that is located within the subdirectory named "first". "first" is located in the root directory.
* Invalid examples include:
* "/.", "/////." - this is not the root directory.
* "/first/." - the first character may not be a '/'.
*/
short int alt_up_sd_card_find_next(char *file_name);
/* This function searches for the next file in a given directory, as specified by the find_first function.
* Inputs:
* file_name - an array to store a name of the file found. Must be 13 bytes long (12 bytes for file name and 1 byte of NULL termination).
* Outputs:
* -1 - end of directory.
* 0 - success
* 2 - No card or incorrect card format.
* 4 - find_first has not been called successfully.
*/
void alt_up_sd_card_set_attributes(short int file_handle, short int attributes);
/* Set file attributes as needed.
*/
short int alt_up_sd_card_get_attributes(short int file_handle);
/* Return file attributes, or -1 if the file_handle is invalid.
*/
short int alt_up_sd_card_read(short int file_handle);
/* Read a single character from the given file. Return -1 if at the end of a file. Any other negative number
* means that the file could not be read. A number between 0 and 255 is an ASCII character read from the SD Card. */
bool alt_up_sd_card_write(short int file_handle, char byte_of_data);
/* Write a single character to a given file. Return true if successful, and false otherwise. */
bool alt_up_sd_card_fclose(short int file_handle);
// This function closes an opened file and saves data to SD Card if necessary.
#else
bool Write_Sector_Data(int sector_index, int partition_offset);
bool Save_Modified_Sector();
bool Read_Sector_Data(int sector_index, int partition_offset);
#endif //SD_RAW_IFACE
//////////////////////////////////////////////////////////////////////////
// file-like operation functions
//////////////////////////////////////////////////////////////////////////
// direct operation functions
/*
* Macros used by alt_sys_init
*/
#define ALTERA_UP_SD_CARD_AVALON_INTERFACE_MOD_INSTANCE(name, device) \
static alt_up_sd_card_dev device = \
{ \
{ \
ALT_LLIST_ENTRY, \
name##_NAME, \
NULL , /* open */ \
NULL , /* close */ \
NULL, /* read */ \
NULL, /* write */ \
NULL , /* lseek */ \
NULL , /* fstat */ \
NULL , /* ioctl */ \
}, \
name##_BASE, \
}
#define ALTERA_UP_SD_CARD_AVALON_INTERFACE_MOD_INIT(name, device) \
{ \
alt_dev_reg(&device.dev); \
}
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ALTERA_UP_SD_CARD_AVALON_INTERFACE_H__ */

193
software/sys_controller_bsp/drivers/inc/altera_avalon_timer.h Normal file
View File

@ -0,0 +1,193 @@
#ifndef __ALT_AVALON_TIMER_H__
#define __ALT_AVALON_TIMER_H__
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
* Altera does not recommend, suggest or require that this reference design *
* file be used in conjunction or combination with any other product. *
******************************************************************************/
#include <string.h>
#include "alt_types.h"
#include "sys/alt_dev.h"
#include "sys/alt_warning.h"
#ifdef __cplusplus
extern "C"
{
#endif /* __cplusplus */
#define __ALT_COUNTER_SIZE(name) name##_COUNTER_SIZE
#define _ALT_COUNTER_SIZE(name) __ALT_COUNTER_SIZE(name)
#define ALT_SYS_CLK_COUNTER_SIZE _ALT_COUNTER_SIZE(ALT_SYS_CLK)
#define ALT_TIMESTAMP_COUNTER_SIZE _ALT_COUNTER_SIZE(ALT_TIMESTAMP_CLK)
#if (ALT_SYS_CLK_COUNTER_SIZE == 64)
#define alt_sysclk_type alt_u64
#else
#define alt_sysclk_type alt_u32
#endif
#if (ALT_TIMESTAMP_COUNTER_SIZE == 64)
#define alt_timestamp_type alt_u64
#else
#define alt_timestamp_type alt_u32
#endif
/*
* The function alt_avalon_timer_sc_init() is the initialisation function for
* the system clock. It registers the timers interrupt handler, and then calls
* the system clock regestration function, alt_sysclk_init().
*/
extern void alt_avalon_timer_sc_init (void* base, alt_u32 irq_controller_id,
alt_u32 irq, alt_u32 freq);
/*
* Variables used to store the timestamp parameters, when the device is to be
* accessed using the high resolution timestamp driver.
*/
extern void* altera_avalon_timer_ts_base;
extern alt_u32 altera_avalon_timer_ts_freq;
/*
* ALTERA_AVALON_TIMER_INSTANCE is the macro used by alt_sys_init() to
* allocate any per device memory that may be required. In this case no
* allocation is necessary.
*/
#define ALTERA_AVALON_TIMER_INSTANCE(name, dev) extern int alt_no_storage
/*
* Macro used to calculate the timer interrupt frequency. Although this is
* somewhat fearsome, when compiled with -O2 it will be resolved at compile
* time to a constant value.
*/
#define ALTERA_AVALON_TIMER_FREQ(freq, period, units) \
strcmp (units, "us") ? \
(strcmp (units, "ms") ? \
(strcmp (units, "s") ? \
((freq + (period - 1))/period) \
: 1) \
: (1000 + (period - 1))/period) \
: ((1000000 + (period - 1))/period)
/*
* Construct macros which contain the base address of the system clock and the
* timestamp device. These are used below to determine which driver to use for
* a given timer.
*/
#define __ALT_CLK_BASE(name) name##_BASE
#define _ALT_CLK_BASE(name) __ALT_CLK_BASE(name)
#define ALT_SYS_CLK_BASE _ALT_CLK_BASE(ALT_SYS_CLK)
#define ALT_TIMESTAMP_CLK_BASE _ALT_CLK_BASE(ALT_TIMESTAMP_CLK)
/*
* If there is no system clock, then the above macro will result in
* ALT_SYS_CLK_BASE being set to none_BASE. We therefore need to provide an
* invalid value for this, so that no timer is wrongly identified as the system
* clock.
*/
#define none_BASE 0xffffffff
/*
* ALTERA_AVALON_TIMER_INIT is the macro used by alt_sys_init() to provide
* the run time initialisation of the device. In this case this translates to
* a call to alt_avalon_timer_sc_init() if the device is the system clock, i.e.
* if it has the name "sysclk".
*
* If the device is not the system clock, then it is used to provide the
* timestamp facility.
*
* To ensure as much as possible is evaluated at compile time, rather than
* compare the name of the device to "/dev/sysclk" using strcmp(), the base
* address of the device is compared to SYSCLK_BASE to determine whether it's
* the system clock. Since the base address of a device must be unique, these
* two aproaches are equivalent.
*
* This macro performs a sanity check to ensure that the interrupt has been
* connected for this device. If not, then an apropriate error message is
* generated at build time.
*/
#define ALTERA_AVALON_TIMER_INIT(name, dev) \
if (name##_BASE == ALT_SYS_CLK_BASE) \
{ \
if (name##_IRQ == ALT_IRQ_NOT_CONNECTED) \
{ \
ALT_LINK_ERROR ("Error: Interrupt not connected for " #dev ". " \
"The system clock driver requires an interrupt to be " \
"connected. Please select an IRQ for this device in " \
"SOPC builder."); \
} \
else \
{ \
alt_avalon_timer_sc_init((void*) name##_BASE, \
name##_IRQ_INTERRUPT_CONTROLLER_ID, \
name##_IRQ, \
ALTERA_AVALON_TIMER_FREQ(name##_FREQ, \
name##_PERIOD, \
name##_PERIOD_UNITS));\
} \
} \
else if (name##_BASE == ALT_TIMESTAMP_CLK_BASE) \
{ \
if (name##_SNAPSHOT) \
{ \
altera_avalon_timer_ts_base = (void*) name##_BASE; \
altera_avalon_timer_ts_freq = name##_FREQ; \
} \
else \
{ \
ALT_LINK_ERROR ("Error: Snapshot register not available for " \
#dev ". " \
"The timestamp driver requires the snapshot register " \
"to be readable. Please enable this register for this " \
"device in SOPC builder."); \
} \
}
/*
*
*/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ALT_AVALON_TIMER_H__ */

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/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
#ifndef __ALTERA_AVALON_TIMER_REGS_H__
#define __ALTERA_AVALON_TIMER_REGS_H__
#include <io.h>
/* STATUS register */
#define ALTERA_AVALON_TIMER_STATUS_REG 0
#define IOADDR_ALTERA_AVALON_TIMER_STATUS(base) \
__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_STATUS_REG)
#define IORD_ALTERA_AVALON_TIMER_STATUS(base) \
IORD(base, ALTERA_AVALON_TIMER_STATUS_REG)
#define IOWR_ALTERA_AVALON_TIMER_STATUS(base, data) \
IOWR(base, ALTERA_AVALON_TIMER_STATUS_REG, data)
#define ALTERA_AVALON_TIMER_STATUS_TO_MSK (0x1)
#define ALTERA_AVALON_TIMER_STATUS_TO_OFST (0)
#define ALTERA_AVALON_TIMER_STATUS_RUN_MSK (0x2)
#define ALTERA_AVALON_TIMER_STATUS_RUN_OFST (1)
/* CONTROL register */
#define ALTERA_AVALON_TIMER_CONTROL_REG 1
#define IOADDR_ALTERA_AVALON_TIMER_CONTROL(base) \
__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_CONTROL_REG)
#define IORD_ALTERA_AVALON_TIMER_CONTROL(base) \
IORD(base, ALTERA_AVALON_TIMER_CONTROL_REG)
#define IOWR_ALTERA_AVALON_TIMER_CONTROL(base, data) \
IOWR(base, ALTERA_AVALON_TIMER_CONTROL_REG, data)
#define ALTERA_AVALON_TIMER_CONTROL_ITO_MSK (0x1)
#define ALTERA_AVALON_TIMER_CONTROL_ITO_OFST (0)
#define ALTERA_AVALON_TIMER_CONTROL_CONT_MSK (0x2)
#define ALTERA_AVALON_TIMER_CONTROL_CONT_OFST (1)
#define ALTERA_AVALON_TIMER_CONTROL_START_MSK (0x4)
#define ALTERA_AVALON_TIMER_CONTROL_START_OFST (2)
#define ALTERA_AVALON_TIMER_CONTROL_STOP_MSK (0x8)
#define ALTERA_AVALON_TIMER_CONTROL_STOP_OFST (3)
/* Period and SnapShot Register for COUNTER_SIZE = 32 */
/*----------------------------------------------------*/
/* PERIODL register */
#define ALTERA_AVALON_TIMER_PERIODL_REG 2
#define IOADDR_ALTERA_AVALON_TIMER_PERIODL(base) \
__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIODL_REG)
#define IORD_ALTERA_AVALON_TIMER_PERIODL(base) \
IORD(base, ALTERA_AVALON_TIMER_PERIODL_REG)
#define IOWR_ALTERA_AVALON_TIMER_PERIODL(base, data) \
IOWR(base, ALTERA_AVALON_TIMER_PERIODL_REG, data)
#define ALTERA_AVALON_TIMER_PERIODL_MSK (0xFFFF)
#define ALTERA_AVALON_TIMER_PERIODL_OFST (0)
/* PERIODH register */
#define ALTERA_AVALON_TIMER_PERIODH_REG 3
#define IOADDR_ALTERA_AVALON_TIMER_PERIODH(base) \
__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIODH_REG)
#define IORD_ALTERA_AVALON_TIMER_PERIODH(base) \
IORD(base, ALTERA_AVALON_TIMER_PERIODH_REG)
#define IOWR_ALTERA_AVALON_TIMER_PERIODH(base, data) \
IOWR(base, ALTERA_AVALON_TIMER_PERIODH_REG, data)
#define ALTERA_AVALON_TIMER_PERIODH_MSK (0xFFFF)
#define ALTERA_AVALON_TIMER_PERIODH_OFST (0)
/* SNAPL register */
#define ALTERA_AVALON_TIMER_SNAPL_REG 4
#define IOADDR_ALTERA_AVALON_TIMER_SNAPL(base) \
__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAPL_REG)
#define IORD_ALTERA_AVALON_TIMER_SNAPL(base) \
IORD(base, ALTERA_AVALON_TIMER_SNAPL_REG)
#define IOWR_ALTERA_AVALON_TIMER_SNAPL(base, data) \
IOWR(base, ALTERA_AVALON_TIMER_SNAPL_REG, data)
#define ALTERA_AVALON_TIMER_SNAPL_MSK (0xFFFF)
#define ALTERA_AVALON_TIMER_SNAPL_OFST (0)
/* SNAPH register */
#define ALTERA_AVALON_TIMER_SNAPH_REG 5
#define IOADDR_ALTERA_AVALON_TIMER_SNAPH(base) \
__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAPH_REG)
#define IORD_ALTERA_AVALON_TIMER_SNAPH(base) \
IORD(base, ALTERA_AVALON_TIMER_SNAPH_REG)
#define IOWR_ALTERA_AVALON_TIMER_SNAPH(base, data) \
IOWR(base, ALTERA_AVALON_TIMER_SNAPH_REG, data)
#define ALTERA_AVALON_TIMER_SNAPH_MSK (0xFFFF)
#define ALTERA_AVALON_TIMER_SNAPH_OFST (0)
/* Period and SnapShot Register for COUNTER_SIZE = 64 */
/*----------------------------------------------------*/
/* PERIOD_0 register */
#define ALTERA_AVALON_TIMER_PERIOD_0_REG 2
#define IOADDR_ALTERA_AVALON_TIMER_PERIOD_0(base) \
__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIOD_0_REG)
#define IORD_ALTERA_AVALON_TIMER_PERIOD_0(base) \
IORD(base, ALTERA_AVALON_TIMER_PERIOD_0_REG)
#define IOWR_ALTERA_AVALON_TIMER_PERIOD_0(base, data) \
IOWR(base, ALTERA_AVALON_TIMER_PERIOD_0_REG, data)
#define ALTERA_AVALON_TIMER_PERIOD_0_MSK (0xFFFF)
#define ALTERA_AVALON_TIMER_PERIOD_0_OFST (0)
/* PERIOD_1 register */
#define ALTERA_AVALON_TIMER_PERIOD_1_REG 3
#define IOADDR_ALTERA_AVALON_TIMER_PERIOD_1(base) \
__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIOD_1_REG)
#define IORD_ALTERA_AVALON_TIMER_PERIOD_1(base) \
IORD(base, ALTERA_AVALON_TIMER_PERIOD_1_REG)
#define IOWR_ALTERA_AVALON_TIMER_PERIOD_1(base, data) \
IOWR(base, ALTERA_AVALON_TIMER_PERIOD_1_REG, data)
#define ALTERA_AVALON_TIMER_PERIOD_1_MSK (0xFFFF)
#define ALTERA_AVALON_TIMER_PERIOD_1_OFST (0)
/* PERIOD_2 register */
#define ALTERA_AVALON_TIMER_PERIOD_2_REG 4
#define IOADDR_ALTERA_AVALON_TIMER_PERIOD_2(base) \
__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIOD_2_REG)
#define IORD_ALTERA_AVALON_TIMER_PERIOD_2(base) \
IORD(base, ALTERA_AVALON_TIMER_PERIOD_2_REG)
#define IOWR_ALTERA_AVALON_TIMER_PERIOD_2(base, data) \
IOWR(base, ALTERA_AVALON_TIMER_PERIOD_2_REG, data)
#define ALTERA_AVALON_TIMER_PERIOD_2_MSK (0xFFFF)
#define ALTERA_AVALON_TIMER_PERIOD_2_OFST (0)
/* PERIOD_3 register */
#define ALTERA_AVALON_TIMER_PERIOD_3_REG 5
#define IOADDR_ALTERA_AVALON_TIMER_PERIOD_3(base) \
__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIOD_3_REG)
#define IORD_ALTERA_AVALON_TIMER_PERIOD_3(base) \
IORD(base, ALTERA_AVALON_TIMER_PERIOD_3_REG)
#define IOWR_ALTERA_AVALON_TIMER_PERIOD_3(base, data) \
IOWR(base, ALTERA_AVALON_TIMER_PERIOD_3_REG, data)
#define ALTERA_AVALON_TIMER_PERIOD_3_MSK (0xFFFF)
#define ALTERA_AVALON_TIMER_PERIOD_3_OFST (0)
/* SNAP_0 register */
#define ALTERA_AVALON_TIMER_SNAP_0_REG 6
#define IOADDR_ALTERA_AVALON_TIMER_SNAP_0(base) \
__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAP_0_REG)
#define IORD_ALTERA_AVALON_TIMER_SNAP_0(base) \
IORD(base, ALTERA_AVALON_TIMER_SNAP_0_REG)
#define IOWR_ALTERA_AVALON_TIMER_SNAP_0(base, data) \
IOWR(base, ALTERA_AVALON_TIMER_SNAP_0_REG, data)
#define ALTERA_AVALON_TIMER_SNAP_0_MSK (0xFFFF)
#define ALTERA_AVALON_TIMER_SNAP_0_OFST (0)
/* SNAP_1 register */
#define ALTERA_AVALON_TIMER_SNAP_1_REG 7
#define IOADDR_ALTERA_AVALON_TIMER_SNAP_1(base) \
__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAP_1_REG)
#define IORD_ALTERA_AVALON_TIMER_SNAP_1(base) \
IORD(base, ALTERA_AVALON_TIMER_SNAP_1_REG)
#define IOWR_ALTERA_AVALON_TIMER_SNAP_1(base, data) \
IOWR(base, ALTERA_AVALON_TIMER_SNAP_1_REG, data)
#define ALTERA_AVALON_TIMER_SNAP_1_MSK (0xFFFF)
#define ALTERA_AVALON_TIMER_SNAP_1_OFST (0)
/* SNAP_2 register */
#define ALTERA_AVALON_TIMER_SNAP_2_REG 8
#define IOADDR_ALTERA_AVALON_TIMER_SNAP_2(base) \
__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAP_2_REG)
#define IORD_ALTERA_AVALON_TIMER_SNAP_2(base) \
IORD(base, ALTERA_AVALON_TIMER_SNAP_2_REG)
#define IOWR_ALTERA_AVALON_TIMER_SNAP_2(base, data) \
IOWR(base, ALTERA_AVALON_TIMER_SNAP_2_REG, data)
#define ALTERA_AVALON_TIMER_SNAP_2_MSK (0xFFFF)
#define ALTERA_AVALON_TIMER_SNAP_2_OFST (0)
/* SNAP_3 register */
#define ALTERA_AVALON_TIMER_SNAP_3_REG 9
#define IOADDR_ALTERA_AVALON_TIMER_SNAP_3(base) \
__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAP_3_REG)
#define IORD_ALTERA_AVALON_TIMER_SNAP_3(base) \
IORD(base, ALTERA_AVALON_TIMER_SNAP_3_REG)
#define IOWR_ALTERA_AVALON_TIMER_SNAP_3(base, data) \
IOWR(base, ALTERA_AVALON_TIMER_SNAP_3_REG, data)
#define ALTERA_AVALON_TIMER_SNAP_3_MSK (0xFFFF)
#define ALTERA_AVALON_TIMER_SNAP_3_OFST (0)
#endif /* __ALTERA_AVALON_TIMER_REGS_H__ */

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/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
* Altera does not recommend, suggest or require that this reference design *
* file be used in conjunction or combination with any other product. *
******************************************************************************/
#include <string.h>
#include "sys/alt_alarm.h"
#include "sys/alt_irq.h"
#include "altera_avalon_timer.h"
#include "altera_avalon_timer_regs.h"
#include "alt_types.h"
#include "sys/alt_log_printf.h"
/*
* alt_avalon_timer_sc_irq() is the interrupt handler used for the system
* clock. This is called periodically when a timer interrupt occurs. The
* function first clears the interrupt condition, and then calls the
* alt_tick() function to notify the system that a timer tick has occurred.
*
* alt_tick() increments the system tick count, and updates any registered
* alarms, see alt_tick.c for further details.
*/
#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
static void alt_avalon_timer_sc_irq (void* base)
#else
static void alt_avalon_timer_sc_irq (void* base, alt_u32 id)
#endif
{
alt_irq_context cpu_sr;
/* clear the interrupt */
IOWR_ALTERA_AVALON_TIMER_STATUS (base, 0);
/*
* Dummy read to ensure IRQ is negated before the ISR returns.
* The control register is read because reading the status
* register has side-effects per the register map documentation.
*/
IORD_ALTERA_AVALON_TIMER_CONTROL (base);
/* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */
ALT_LOG_SYS_CLK_HEARTBEAT();
/*
* Notify the system of a clock tick. disable interrupts
* during this time to safely support ISR preemption
*/
cpu_sr = alt_irq_disable_all();
alt_tick ();
alt_irq_enable_all(cpu_sr);
}
/*
* alt_avalon_timer_sc_init() is called to initialise the timer that will be
* used to provide the periodic system clock. This is called from the
* auto-generated alt_sys_init() function.
*/
void alt_avalon_timer_sc_init (void* base, alt_u32 irq_controller_id,
alt_u32 irq, alt_u32 freq)
{
/* set the system clock frequency */
alt_sysclk_init (freq);
/* set to free running mode */
IOWR_ALTERA_AVALON_TIMER_CONTROL (base,
ALTERA_AVALON_TIMER_CONTROL_ITO_MSK |
ALTERA_AVALON_TIMER_CONTROL_CONT_MSK |
ALTERA_AVALON_TIMER_CONTROL_START_MSK);
/* register the interrupt handler, and enable the interrupt */
#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
alt_ic_isr_register(irq_controller_id, irq, alt_avalon_timer_sc_irq,
base, NULL);
#else
alt_irq_register (irq, base, alt_avalon_timer_sc_irq);
#endif
}

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/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
* Altera does not recommend, suggest or require that this reference design *
* file be used in conjunction or combination with any other product. *
******************************************************************************/
#include <string.h>
#include "system.h"
#include "sys/alt_timestamp.h"
#include "altera_avalon_timer.h"
#include "altera_avalon_timer_regs.h"
#include "alt_types.h"
/*
* These functions are only available if a timestamp device has been selected
* for this system.
*/
#if (ALT_TIMESTAMP_CLK_BASE != none_BASE)
/*
* The function alt_timestamp_start() can be called at application level to
* initialise the timestamp facility. In this case the period register is
* set to full scale, i.e. 0xffffffff, and then started running. Note that
* the period register may not be writable, depending on the hardware
* configuration, in which case this function does not reset the period.
*
* The timer is not run in continuous mode, so that the user can detect timer
* roll-over, i.e. alt_timestamp() returns 0.
*
* The return value of this function is 0 upon sucess and -1 if in timestamp
* device has not been registered.
*/
int alt_timestamp_start(void)
{
void* base = altera_avalon_timer_ts_base;
if (!altera_avalon_timer_ts_freq)
{
return -1;
}
else
{
if(ALT_TIMESTAMP_COUNTER_SIZE == 64) {
IOWR_ALTERA_AVALON_TIMER_CONTROL (base,ALTERA_AVALON_TIMER_CONTROL_STOP_MSK);
IOWR_ALTERA_AVALON_TIMER_PERIOD_0 (base, 0xFFFF);
IOWR_ALTERA_AVALON_TIMER_PERIOD_1 (base, 0xFFFF);;
IOWR_ALTERA_AVALON_TIMER_PERIOD_2 (base, 0xFFFF);
IOWR_ALTERA_AVALON_TIMER_PERIOD_3 (base, 0xFFFF);
IOWR_ALTERA_AVALON_TIMER_CONTROL (base, ALTERA_AVALON_TIMER_CONTROL_START_MSK);
} else {
IOWR_ALTERA_AVALON_TIMER_CONTROL (base,ALTERA_AVALON_TIMER_CONTROL_STOP_MSK);
IOWR_ALTERA_AVALON_TIMER_PERIODL (base, 0xFFFF);
IOWR_ALTERA_AVALON_TIMER_PERIODH (base, 0xFFFF);
IOWR_ALTERA_AVALON_TIMER_CONTROL (base, ALTERA_AVALON_TIMER_CONTROL_START_MSK);
}
}
return 0;
}
/*
* alt_timestamp() returns the current timestamp count. In the event that
* the timer has run full period, or there is no timestamp available, this
* function return -1.
*
* The returned timestamp counts up from the last time the period register
* was reset.
*/
alt_timestamp_type alt_timestamp(void)
{
void* base = altera_avalon_timer_ts_base;
if (!altera_avalon_timer_ts_freq)
{
#if (ALT_TIMESTAMP_COUNTER_SIZE == 64)
return 0xFFFFFFFFFFFFFFFFULL;
#else
return 0xFFFFFFFF;
#endif
}
else
{
#if (ALT_TIMESTAMP_COUNTER_SIZE == 64)
IOWR_ALTERA_AVALON_TIMER_SNAP_0 (base, 0);
alt_timestamp_type snap_0 = IORD_ALTERA_AVALON_TIMER_SNAP_0(base) & ALTERA_AVALON_TIMER_SNAP_0_MSK;
alt_timestamp_type snap_1 = IORD_ALTERA_AVALON_TIMER_SNAP_1(base) & ALTERA_AVALON_TIMER_SNAP_1_MSK;
alt_timestamp_type snap_2 = IORD_ALTERA_AVALON_TIMER_SNAP_2(base) & ALTERA_AVALON_TIMER_SNAP_2_MSK;
alt_timestamp_type snap_3 = IORD_ALTERA_AVALON_TIMER_SNAP_3(base) & ALTERA_AVALON_TIMER_SNAP_3_MSK;
return (0xFFFFFFFFFFFFFFFFULL - ( (snap_3 << 48) | (snap_2 << 32) | (snap_1 << 16) | (snap_0) ));
#else
IOWR_ALTERA_AVALON_TIMER_SNAPL (base, 0);
alt_timestamp_type lower = IORD_ALTERA_AVALON_TIMER_SNAPL(base) & ALTERA_AVALON_TIMER_SNAPL_MSK;
alt_timestamp_type upper = IORD_ALTERA_AVALON_TIMER_SNAPH(base) & ALTERA_AVALON_TIMER_SNAPH_MSK;
return (0xFFFFFFFF - ((upper << 16) | lower));
#endif
}
}
/*
* Return the number of timestamp ticks per second. This will be 0 if no
* timestamp device has been registered.
*/
alt_u32 alt_timestamp_freq(void)
{
return altera_avalon_timer_ts_freq;
}
#endif /* timestamp available */

83
ip/nios2_hw_crc/HAL/inc/ci_crc.h → software/sys_controller_bsp/drivers/src/altera_avalon_timer_vars.c
View File

@ -1,38 +1,45 @@
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* Altera does not recommend, suggest or require that this reference design *
* file be used in conjunction or combination with any other product. *
******************************************************************************/
#ifndef _CRCCI_H_
#define _CRCCI_H_
unsigned long crcCI(unsigned char * input_data, unsigned long input_data_length, int do_initialize);
#endif //_CRCCI_H_
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
* Altera does not recommend, suggest or require that this reference design *
* file be used in conjunction or combination with any other product. *
******************************************************************************/
#include <string.h>
#include "altera_avalon_timer.h"
#include "alt_types.h"
/*
* Variables used to store the timestamp parameters. These are initialised
* from alt_sys_init() using the ALTERA_AVALON_TIMER_INIT macro
* defined in altera_avalon_timer.h.
*/
void* altera_avalon_timer_ts_base = (void*) 0;
alt_u32 altera_avalon_timer_ts_freq = 0;

BIN
software/sys_controller_bsp/libhal_bsp.a
View File

Binary file not shown.

10
software/sys_controller_bsp/linker.h
View File

@ -4,7 +4,7 @@
* Machine generated for CPU 'nios2_qsys_0' in SOPC Builder design 'sys'
* SOPC Builder design path: ../../sys.sopcinfo
*
* Generated: Sun Oct 16 12:18:06 EEST 2016
* Generated: Fri Oct 05 19:59:02 EEST 2018
*/
/*
@ -65,11 +65,11 @@
*
*/
#define EPCQ_CONTROLLER_0_AVL_MEM_REGION_BASE 0x0
#define EPCQ_CONTROLLER_0_AVL_MEM_REGION_BASE 0x800000
#define EPCQ_CONTROLLER_0_AVL_MEM_REGION_SPAN 8388608
#define ONCHIP_MEMORY2_0_REGION_BASE 0x810020
#define ONCHIP_MEMORY2_0_REGION_SPAN 40928
#define RESET_REGION_BASE 0x810000
#define ONCHIP_MEMORY2_0_REGION_BASE 0x10020
#define ONCHIP_MEMORY2_0_REGION_SPAN 36832
#define RESET_REGION_BASE 0x10000
#define RESET_REGION_SPAN 32

52
software/sys_controller_bsp/linker.x
View File

@ -4,7 +4,7 @@
* Machine generated for CPU 'nios2_qsys_0' in SOPC Builder design 'sys'
* SOPC Builder design path: ../../sys.sopcinfo
*
* Generated: Sun Oct 16 12:18:06 EEST 2016
* Generated: Fri Oct 05 19:59:02 EEST 2018
*/
/*
@ -50,14 +50,14 @@
MEMORY
{
epcq_controller_0_avl_mem : ORIGIN = 0x0, LENGTH = 8388608
reset : ORIGIN = 0x810000, LENGTH = 32
onchip_memory2_0 : ORIGIN = 0x810020, LENGTH = 40928
reset : ORIGIN = 0x10000, LENGTH = 32
onchip_memory2_0 : ORIGIN = 0x10020, LENGTH = 36832
epcq_controller_0_avl_mem : ORIGIN = 0x800000, LENGTH = 8388608
}
/* Define symbols for each memory base-address */
__alt_mem_epcq_controller_0_avl_mem = 0x0;
__alt_mem_onchip_memory2_0 = 0x810000;
__alt_mem_onchip_memory2_0 = 0x10000;
__alt_mem_epcq_controller_0_avl_mem = 0x800000;
OUTPUT_FORMAT( "elf32-littlenios2",
"elf32-littlenios2",
@ -309,24 +309,7 @@ SECTIONS
*
*/
.epcq_controller_0_avl_mem : AT ( LOADADDR (.bss) + SIZEOF (.bss) )
{
PROVIDE (_alt_partition_epcq_controller_0_avl_mem_start = ABSOLUTE(.));
*(.epcq_controller_0_avl_mem .epcq_controller_0_avl_mem. epcq_controller_0_avl_mem.*)
. = ALIGN(4);
PROVIDE (_alt_partition_epcq_controller_0_avl_mem_end = ABSOLUTE(.));
} > epcq_controller_0_avl_mem
PROVIDE (_alt_partition_epcq_controller_0_avl_mem_load_addr = LOADADDR(.epcq_controller_0_avl_mem));
/*
*
* This section's LMA is set to the .text region.
* crt0 will copy to this section's specified mapped region virtual memory address (VMA)
*
*/
.onchip_memory2_0 LOADADDR (.epcq_controller_0_avl_mem) + SIZEOF (.epcq_controller_0_avl_mem) : AT ( LOADADDR (.epcq_controller_0_avl_mem) + SIZEOF (.epcq_controller_0_avl_mem) )
.onchip_memory2_0 LOADADDR (.bss) + SIZEOF (.bss) : AT ( LOADADDR (.bss) + SIZEOF (.bss) )
{
PROVIDE (_alt_partition_onchip_memory2_0_start = ABSOLUTE(.));
*(.onchip_memory2_0 .onchip_memory2_0. onchip_memory2_0.*)
@ -339,6 +322,23 @@ SECTIONS
PROVIDE (_alt_partition_onchip_memory2_0_load_addr = LOADADDR(.onchip_memory2_0));
/*
*
* This section's LMA is set to the .text region.
* crt0 will copy to this section's specified mapped region virtual memory address (VMA)
*
*/
.epcq_controller_0_avl_mem : AT ( LOADADDR (.onchip_memory2_0) + SIZEOF (.onchip_memory2_0) )
{
PROVIDE (_alt_partition_epcq_controller_0_avl_mem_start = ABSOLUTE(.));
*(.epcq_controller_0_avl_mem .epcq_controller_0_avl_mem. epcq_controller_0_avl_mem.*)
. = ALIGN(4);
PROVIDE (_alt_partition_epcq_controller_0_avl_mem_end = ABSOLUTE(.));
} > epcq_controller_0_avl_mem
PROVIDE (_alt_partition_epcq_controller_0_avl_mem_load_addr = LOADADDR(.epcq_controller_0_avl_mem));
/*
* Stabs debugging sections.
*
@ -386,7 +386,7 @@ SECTIONS
/*
* Don't override this, override the __alt_stack_* symbols instead.
*/
__alt_data_end = 0x81a000;
__alt_data_end = 0x19000;
/*
* The next two symbols define the location of the default stack. You can
@ -402,4 +402,4 @@ PROVIDE( __alt_stack_limit = __alt_stack_base );
* Override this symbol to put the heap in a different memory.
*/
PROVIDE( __alt_heap_start = end );
PROVIDE( __alt_heap_limit = 0x81a000 );
PROVIDE( __alt_heap_limit = 0x19000 );

20
software/sys_controller_bsp/mem_init.mk
View File

@ -161,7 +161,7 @@ ACDS_VERSION := 17.1
SIM_OPTIMIZE ?= 0
# The CPU reset address as needed by elf2flash
RESET_ADDRESS ?= 0x00810000
RESET_ADDRESS ?= 0x00010000
# The specific Nios II ELF file format to use.
NIOS2_ELF_FORMAT ?= elf32-littlenios2
@ -175,8 +175,8 @@ MEM_0 := epcq_controller_0
$(MEM_0)_NAME := epcq_controller_0
HEX_FILES += $(MEM_INIT_DIR)/$(MEM_0).hex
MEM_INIT_INSTALL_FILES += $(MEM_INIT_INSTALL_DIR)/$(MEM_0).hex
$(MEM_0)_START := 0x00000000
$(MEM_0)_END := 0x007fffff
$(MEM_0)_START := 0x00800000
$(MEM_0)_END := 0x00ffffff
$(MEM_0)_SPAN := 0x00800000
$(MEM_0)_HIERARCHICAL_PATH := epcq_controller_0
$(MEM_0)_WIDTH := 32
@ -198,9 +198,9 @@ DAT_FILES += $(HDL_SIM_DIR)/$(MEM_1).dat
HDL_SIM_INSTALL_FILES += $(HDL_SIM_INSTALL_DIR)/$(MEM_1).dat
SYM_FILES += $(HDL_SIM_DIR)/$(MEM_1).sym
HDL_SIM_INSTALL_FILES += $(HDL_SIM_INSTALL_DIR)/$(MEM_1).sym
$(MEM_1)_START := 0x00810000
$(MEM_1)_END := 0x00819fff
$(MEM_1)_SPAN := 0x0000a000
$(MEM_1)_START := 0x00010000
$(MEM_1)_END := 0x00018fff
$(MEM_1)_SPAN := 0x00009000
$(MEM_1)_HIERARCHICAL_PATH := onchip_memory2_0
$(MEM_1)_WIDTH := 32
$(MEM_1)_HEX_DATA_WIDTH := 32
@ -304,10 +304,10 @@ ELF_TO_HEX_CMD = $(strip $(if $(flash_mem_boot_loader_flag), \
$(ELF_TO_HEX_CMD_NO_BOOTLOADER) \
))
$(HEX_FILES): %.hex: $(ELF)
$(post-process-info)
@$(MKDIR) $(@D)
$(ELF_TO_HEX_CMD)
#$(HEX_FILES): %.hex: $(ELF)
# $(post-process-info)
# @$(MKDIR) $(@D)
# $(ELF_TO_HEX_CMD)
$(SYM_FILES): %.sym: $(ELF)
$(post-process-info)

10
software/sys_controller_bsp/memory.gdb
View File

@ -3,7 +3,7 @@
# Machine generated for CPU 'nios2_qsys_0' in SOPC Builder design 'sys'
# SOPC Builder design path: ../../sys.sopcinfo
#
# Generated: Sun Oct 16 12:18:06 EEST 2016
# Generated: Fri Oct 05 19:59:02 EEST 2018
# DO NOT MODIFY THIS FILE
#
@ -46,8 +46,8 @@
# The cache attribute is specified which improves GDB performance
# by allowing GDB to cache memory contents on the host.
# epcq_controller_0_avl_mem
memory 0x0 0x800000 cache
# onchip_memory2_0
memory 0x810000 0x81a000 cache
memory 0x10000 0x19000 cache
# epcq_controller_0_avl_mem
memory 0x800000 0x1000000 cache

54
software/sys_controller_bsp/settings.bsp
View File

@ -2,8 +2,8 @@
<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
<BspType>hal</BspType>
<BspVersion>default</BspVersion>
<BspGeneratedTimeStamp>Sep 25, 2018 9:18:49 PM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1537899529022</BspGeneratedUnixTimeStamp>
<BspGeneratedTimeStamp>Oct 5, 2018 8:21:01 PM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1538758741996</BspGeneratedUnixTimeStamp>
<BspGeneratedLocation>./</BspGeneratedLocation>
<BspSettingsFile>settings.bsp</BspSettingsFile>
<SopcDesignFile>../../sys.sopcinfo</SopcDesignFile>
@ -898,101 +898,101 @@
<Enabled>false</Enabled>
<Group xsi:nil="true" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"/>
</Setting>
<MemoryMap>
<slaveDescriptor>epcq_controller_0_avl_mem</slaveDescriptor>
<addressRange>0x00000000 - 0x007FFFFF</addressRange>
<addressSpan>8388608</addressSpan>
<attributes>flash, memory, non-volatile</attributes>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>onchip_memory2_0</slaveDescriptor>
<addressRange>0x00810000 - 0x00819FFF</addressRange>
<addressRange>0x00010000 - 0x00019FFF</addressRange>
<addressSpan>40960</addressSpan>
<attributes>memory</attributes>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>timer_0</slaveDescriptor>
<addressRange>0x00821000 - 0x0082101F</addressRange>
<addressRange>0x00020000 - 0x0002001F</addressRange>
<addressSpan>32</addressSpan>
<attributes>timer</attributes>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>jtag_uart_0</slaveDescriptor>
<addressRange>0x00020020 - 0x00020027</addressRange>
<addressSpan>8</addressSpan>
<attributes>printable</attributes>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>epcq_controller_0_avl_csr</slaveDescriptor>
<addressRange>0x00821020 - 0x0082103F</addressRange>
<addressRange>0x00020100 - 0x0002011F</addressRange>
<addressSpan>32</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>i2c_opencores_1</slaveDescriptor>
<addressRange>0x00821040 - 0x0082105F</addressRange>
<addressRange>0x00021020 - 0x0002103F</addressRange>
<addressSpan>32</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>i2c_opencores_0</slaveDescriptor>
<addressRange>0x00821060 - 0x0082107F</addressRange>
<addressRange>0x00021040 - 0x0002105F</addressRange>
<addressSpan>32</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>pio_8</slaveDescriptor>
<addressRange>0x00821080 - 0x0082108F</addressRange>
<addressRange>0x00021060 - 0x0002106F</addressRange>
<addressSpan>16</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>pio_7</slaveDescriptor>
<addressRange>0x00821090 - 0x0082109F</addressRange>
<addressRange>0x00021070 - 0x0002107F</addressRange>
<addressSpan>16</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>pio_6</slaveDescriptor>
<addressRange>0x008210A0 - 0x008210AF</addressRange>
<addressRange>0x00021080 - 0x0002108F</addressRange>
<addressSpan>16</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>pio_5</slaveDescriptor>
<addressRange>0x008210B0 - 0x008210BF</addressRange>
<addressRange>0x00021090 - 0x0002109F</addressRange>
<addressSpan>16</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>pio_4</slaveDescriptor>
<addressRange>0x008210C0 - 0x008210CF</addressRange>
<addressRange>0x000210A0 - 0x000210AF</addressRange>
<addressSpan>16</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>pio_3</slaveDescriptor>
<addressRange>0x008210D0 - 0x008210DF</addressRange>
<addressRange>0x000210B0 - 0x000210BF</addressRange>
<addressSpan>16</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>pio_2</slaveDescriptor>
<addressRange>0x008210E0 - 0x008210EF</addressRange>
<addressRange>0x000210C0 - 0x000210CF</addressRange>
<addressSpan>16</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>pio_1</slaveDescriptor>
<addressRange>0x008210F0 - 0x008210FF</addressRange>
<addressRange>0x000210D0 - 0x000210DF</addressRange>
<addressSpan>16</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>pio_0</slaveDescriptor>
<addressRange>0x00821100 - 0x0082110F</addressRange>
<addressRange>0x000210E0 - 0x000210EF</addressRange>
<addressSpan>16</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap>
<slaveDescriptor>jtag_uart_0</slaveDescriptor>
<addressRange>0x00821110 - 0x00821117</addressRange>
<addressSpan>8</addressSpan>
<attributes>printable</attributes>
<slaveDescriptor>epcq_controller_0_avl_mem</slaveDescriptor>
<addressRange>0x00800000 - 0x00FFFFFF</addressRange>
<addressSpan>8388608</addressSpan>
<attributes>flash, memory, non-volatile</attributes>
</MemoryMap>
<LinkerSection>
<sectionName>.text</sectionName>
@ -1018,4 +1018,4 @@
<sectionName>.stack</sectionName>
<regionName>onchip_memory2_0</regionName>
</LinkerSection>
</sch:Settings>
</sch:Settings>

58
software/sys_controller_bsp/system.h
View File

@ -4,7 +4,7 @@
* Machine generated for CPU 'nios2_qsys_0' in SOPC Builder design 'sys'
* SOPC Builder design path: ../../sys.sopcinfo
*
* Generated: Sun Mar 25 16:51:03 EEST 2018
* Generated: Fri Oct 05 19:59:02 EEST 2018
*/
/*
@ -62,7 +62,7 @@
#define ALT_CPU_ARCHITECTURE "altera_nios2_gen2"
#define ALT_CPU_BIG_ENDIAN 0
#define ALT_CPU_BREAK_ADDR 0x00820820
#define ALT_CPU_BREAK_ADDR 0x00000820
#define ALT_CPU_CPU_ARCH_NIOS2_R1
#define ALT_CPU_CPU_FREQ 27000000u
#define ALT_CPU_CPU_ID_SIZE 1
@ -72,7 +72,7 @@
#define ALT_CPU_DCACHE_LINE_SIZE 0
#define ALT_CPU_DCACHE_LINE_SIZE_LOG2 0
#define ALT_CPU_DCACHE_SIZE 0
#define ALT_CPU_EXCEPTION_ADDR 0x00810020
#define ALT_CPU_EXCEPTION_ADDR 0x00010020
#define ALT_CPU_FLASH_ACCELERATOR_LINES 0
#define ALT_CPU_FLASH_ACCELERATOR_LINE_SIZE 0
#define ALT_CPU_FLUSHDA_SUPPORTED
@ -87,10 +87,10 @@
#define ALT_CPU_ICACHE_LINE_SIZE 0
#define ALT_CPU_ICACHE_LINE_SIZE_LOG2 0
#define ALT_CPU_ICACHE_SIZE 0
#define ALT_CPU_INST_ADDR_WIDTH 0x18
#define ALT_CPU_INST_ADDR_WIDTH 0x11
#define ALT_CPU_NAME "nios2_qsys_0"
#define ALT_CPU_OCI_VERSION 1
#define ALT_CPU_RESET_ADDR 0x00810000
#define ALT_CPU_RESET_ADDR 0x00010000
/*
@ -99,7 +99,7 @@
*/
#define NIOS2_BIG_ENDIAN 0
#define NIOS2_BREAK_ADDR 0x00820820
#define NIOS2_BREAK_ADDR 0x00000820
#define NIOS2_CPU_ARCH_NIOS2_R1
#define NIOS2_CPU_FREQ 27000000u
#define NIOS2_CPU_ID_SIZE 1
@ -109,7 +109,7 @@
#define NIOS2_DCACHE_LINE_SIZE 0
#define NIOS2_DCACHE_LINE_SIZE_LOG2 0
#define NIOS2_DCACHE_SIZE 0
#define NIOS2_EXCEPTION_ADDR 0x00810020
#define NIOS2_EXCEPTION_ADDR 0x00010020
#define NIOS2_FLASH_ACCELERATOR_LINES 0
#define NIOS2_FLASH_ACCELERATOR_LINE_SIZE 0
#define NIOS2_FLUSHDA_SUPPORTED
@ -123,9 +123,9 @@
#define NIOS2_ICACHE_LINE_SIZE 0
#define NIOS2_ICACHE_LINE_SIZE_LOG2 0
#define NIOS2_ICACHE_SIZE 0
#define NIOS2_INST_ADDR_WIDTH 0x18
#define NIOS2_INST_ADDR_WIDTH 0x11
#define NIOS2_OCI_VERSION 1
#define NIOS2_RESET_ADDR 0x00810000
#define NIOS2_RESET_ADDR 0x00010000
/*
@ -140,7 +140,7 @@
#define ALT_CI_NIOS_CUSTOM_INSTR_BITSWAP_0_N 0x9
//#define ALT_CI_NIOS_CUSTOM_INSTR_ENDIANCONVERTER_0(A) __builtin_custom_ini(ALT_CI_NIOS_CUSTOM_INSTR_ENDIANCONVERTER_0_N,(A))
#define ALT_CI_NIOS_CUSTOM_INSTR_ENDIANCONVERTER_0_N 0x8
#define ALT_CI_NIOS2_HW_CRC32_0(n,A) n
#define ALT_CI_NIOS_CUSTOM_INSTR_BITSWAP_0(A) A
#define ALT_CI_NIOS_CUSTOM_INSTR_ENDIANCONVERTER_0(A) A
@ -179,19 +179,19 @@
#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1
#define ALT_NUM_INTERRUPT_CONTROLLERS 1
#define ALT_STDERR "/dev/jtag_uart_0"
#define ALT_STDERR_BASE 0x821110
#define ALT_STDERR_BASE 0x20020
#define ALT_STDERR_DEV jtag_uart_0
#define ALT_STDERR_IS_JTAG_UART
#define ALT_STDERR_PRESENT
#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
#define ALT_STDIN "/dev/jtag_uart_0"
#define ALT_STDIN_BASE 0x821110
#define ALT_STDIN_BASE 0x20020
#define ALT_STDIN_DEV jtag_uart_0
#define ALT_STDIN_IS_JTAG_UART
#define ALT_STDIN_PRESENT
#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
#define ALT_STDOUT "/dev/jtag_uart_0"
#define ALT_STDOUT_BASE 0x821110
#define ALT_STDOUT_BASE 0x20020
#define ALT_STDOUT_DEV jtag_uart_0
#define ALT_STDOUT_IS_JTAG_UART
#define ALT_STDOUT_PRESENT
@ -205,7 +205,7 @@
*/
#define ALT_MODULE_CLASS_epcq_controller_0_avl_csr altera_epcq_controller_mod
#define EPCQ_CONTROLLER_0_AVL_CSR_BASE 0x821020
#define EPCQ_CONTROLLER_0_AVL_CSR_BASE 0x20100
#define EPCQ_CONTROLLER_0_AVL_CSR_FLASH_TYPE "EPCS64"
#define EPCQ_CONTROLLER_0_AVL_CSR_IRQ 2
#define EPCQ_CONTROLLER_0_AVL_CSR_IRQ_INTERRUPT_CONTROLLER_ID 0
@ -225,7 +225,7 @@
*/
#define ALT_MODULE_CLASS_epcq_controller_0_avl_mem altera_epcq_controller_mod
#define EPCQ_CONTROLLER_0_AVL_MEM_BASE 0x0
#define EPCQ_CONTROLLER_0_AVL_MEM_BASE 0x800000
#define EPCQ_CONTROLLER_0_AVL_MEM_FLASH_TYPE "EPCS64"
#define EPCQ_CONTROLLER_0_AVL_MEM_IRQ -1
#define EPCQ_CONTROLLER_0_AVL_MEM_IRQ_INTERRUPT_CONTROLLER_ID -1
@ -255,7 +255,7 @@
*/
#define ALT_MODULE_CLASS_i2c_opencores_0 i2c_opencores
#define I2C_OPENCORES_0_BASE 0x821060
#define I2C_OPENCORES_0_BASE 0x21040
#define I2C_OPENCORES_0_IRQ 3
#define I2C_OPENCORES_0_IRQ_INTERRUPT_CONTROLLER_ID 0
#define I2C_OPENCORES_0_NAME "/dev/i2c_opencores_0"
@ -269,7 +269,7 @@
*/
#define ALT_MODULE_CLASS_i2c_opencores_1 i2c_opencores
#define I2C_OPENCORES_1_BASE 0x821040
#define I2C_OPENCORES_1_BASE 0x21020
#define I2C_OPENCORES_1_IRQ 4
#define I2C_OPENCORES_1_IRQ_INTERRUPT_CONTROLLER_ID 0
#define I2C_OPENCORES_1_NAME "/dev/i2c_opencores_1"
@ -283,7 +283,7 @@
*/
#define ALT_MODULE_CLASS_jtag_uart_0 altera_avalon_jtag_uart
#define JTAG_UART_0_BASE 0x821110
#define JTAG_UART_0_BASE 0x20020
#define JTAG_UART_0_IRQ 1
#define JTAG_UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0
#define JTAG_UART_0_NAME "/dev/jtag_uart_0"
@ -303,7 +303,7 @@
#define ALT_MODULE_CLASS_onchip_memory2_0 altera_avalon_onchip_memory2
#define ONCHIP_MEMORY2_0_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define ONCHIP_MEMORY2_0_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define ONCHIP_MEMORY2_0_BASE 0x810000
#define ONCHIP_MEMORY2_0_BASE 0x10000
#define ONCHIP_MEMORY2_0_CONTENTS_INFO ""
#define ONCHIP_MEMORY2_0_DUAL_PORT 0
#define ONCHIP_MEMORY2_0_GUI_RAM_BLOCK_TYPE "AUTO"
@ -330,7 +330,7 @@
*/
#define ALT_MODULE_CLASS_pio_0 altera_avalon_pio
#define PIO_0_BASE 0x821100
#define PIO_0_BASE 0x210e0
#define PIO_0_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_0_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PIO_0_CAPTURE 0
@ -357,7 +357,7 @@
*/
#define ALT_MODULE_CLASS_pio_1 altera_avalon_pio
#define PIO_1_BASE 0x8210f0
#define PIO_1_BASE 0x210d0
#define PIO_1_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_1_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PIO_1_CAPTURE 0
@ -384,7 +384,7 @@
*/
#define ALT_MODULE_CLASS_pio_2 altera_avalon_pio
#define PIO_2_BASE 0x8210e0
#define PIO_2_BASE 0x210c0
#define PIO_2_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_2_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PIO_2_CAPTURE 0
@ -411,7 +411,7 @@
*/
#define ALT_MODULE_CLASS_pio_3 altera_avalon_pio
#define PIO_3_BASE 0x8210d0
#define PIO_3_BASE 0x210b0
#define PIO_3_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_3_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PIO_3_CAPTURE 0
@ -438,7 +438,7 @@
*/
#define ALT_MODULE_CLASS_pio_4 altera_avalon_pio
#define PIO_4_BASE 0x8210c0
#define PIO_4_BASE 0x210a0
#define PIO_4_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_4_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PIO_4_CAPTURE 0
@ -465,7 +465,7 @@
*/
#define ALT_MODULE_CLASS_pio_5 altera_avalon_pio
#define PIO_5_BASE 0x8210b0
#define PIO_5_BASE 0x21090
#define PIO_5_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_5_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PIO_5_CAPTURE 0
@ -492,7 +492,7 @@
*/
#define ALT_MODULE_CLASS_pio_6 altera_avalon_pio
#define PIO_6_BASE 0x8210a0
#define PIO_6_BASE 0x21080
#define PIO_6_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_6_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PIO_6_CAPTURE 0
@ -519,7 +519,7 @@
*/
#define ALT_MODULE_CLASS_pio_7 altera_avalon_pio
#define PIO_7_BASE 0x821090
#define PIO_7_BASE 0x21070
#define PIO_7_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_7_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PIO_7_CAPTURE 0
@ -546,7 +546,7 @@
*/
#define ALT_MODULE_CLASS_pio_8 altera_avalon_pio
#define PIO_8_BASE 0x821080
#define PIO_8_BASE 0x21060
#define PIO_8_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_8_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PIO_8_CAPTURE 0
@ -574,7 +574,7 @@
#define ALT_MODULE_CLASS_timer_0 altera_avalon_timer
#define TIMER_0_ALWAYS_RUN 0
#define TIMER_0_BASE 0x821000
#define TIMER_0_BASE 0x20000
#define TIMER_0_COUNTER_SIZE 32
#define TIMER_0_FIXED_PERIOD 0
#define TIMER_0_FREQ 27000000

764
sys.qsys
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7440
sys.sopcinfo
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53
tools/bin2hex.c Normal file
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@ -0,0 +1,53 @@
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <unistd.h>
#define MEMBLK 1024
int main(int argc, char **argv)
{
unsigned char block[4];
unsigned int csum;
int fd_i;
FILE *fd_o;
struct stat fileinfo;
unsigned int i;
if (argc != 3) {
printf("usage: %s binfile hexfile\n", argv[0]);
return -1;
}
if ((fd_i = open(argv[1], O_RDONLY)) == -1 || fstat(fd_i, &fileinfo) == -1) {
printf("Couldn't open file\n");
return -1;
}
printf("size: %u bytes\n", fileinfo.st_size);
if ((fd_o = fopen(argv[2], "w")) == NULL) {
printf("invalid outfile\n");
return -1;
}
for (i=0; i<fileinfo.st_size; i+=4) {
read(fd_i, (void*)block, 4);
csum = 0x04+((i/4)>>8)+((i/4)&0xff)+block[3]+block[2]+block[1]+block[0];
csum &= 0xff;
csum = (~csum+1)&0xff;
fprintf(fd_o, ":04%.4X00%.2X%.2X%.2X%.2X%.2X\n", i/4, block[3],block[2],block[1],block[0],csum);
}
fprintf(fd_o, ":00000001FF\n");
fclose(fd_o);
close(fd_i);
return 0;
}