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clean up and update README

This commit is contained in:
marqs 2018-10-08 00:37:42 +03:00
parent e8d5097ecb
commit 7914a2ee83
11 changed files with 6504 additions and 6427 deletions
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59
README.md
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@ -12,6 +12,7 @@ Requirements for building and debugging firmware
* Software
* [Altera Quartus II + Cyclone IV support](http://dl.altera.com/?edition=lite) (v 16.1 or higher - free Lite Edition suffices)
* [RISC-V GNU Compiler Toolchain](https://github.com/riscv/riscv-gnu-toolchain)
* GCC (or another C compiler) for host architecture (for building a SD card image)
* Make
* [iconv](https://en.wikipedia.org/wiki/Iconv) (for building with JP lang menu)
@ -19,31 +20,33 @@ Requirements for building and debugging firmware
Architecture
------------------------------
* [Reference board schematics](https://www.niksula.hut.fi/~mhiienka/ossc/diy-v1.5/ossc_v1.5-diy_schematic.pdf)
* [Reference board schematics](https://github.com/marqs85/ossc_pcb/raw/v1.6/ossc_board.pdf)
* [Reference PCB project](https://github.com/marqs85/ossc_pcb)
SW toolchain build procedure
--------------------------
1. Download, configure, build and install RISC-V toolchain with Newlib + multilib support:
~~~~
git clone --recursive https://github.com/riscv/riscv-gnu-toolchain
cd riscv-gnu-toolchain
./configure --prefix=/opt/riscv --enable-multilib
make
make install
~~~~
2. Compile custom binary to IHEX converter:
~~~~
gcc tools/bin2hex.c -o tools/bin2hex
~~~~
Building software image
--------------------------
1. Enter BSP directory:
~~~~
cd software/sys_controller_bsp
~~~~
2. (Optionally) edit BSP settings:
~~~~
nios2-bsp-editor
~~~~
3. Generate BSP:
~~~~
nios2-bsp-generate-files --bsp-dir . --settings settings.bsp
~~~~
NOTE: the previous step must be done every time after RTL/bitstream is built
4. Enter software root directory:
1. Enter software root directory:
~~~~
cd software/sys_controller
~~~~
5. Build SW for target configuration:
2. Build SW for target configuration:
~~~~
make [OPTIONS] [TARGET]
~~~~
@ -52,21 +55,25 @@ OPTIONS may include following definitions:
* ENABLE_AUDIO=y (Includes audio setup code for v1.6 PCB / DIY audio add-on board)
TARGET is typically one of the following:
* all (Default target. Compiles an ELF for direct downloading to Nios2 during testing)
* all (Default target. Compiles an ELF for direct downloading to CPU during testing)
* generate_hex (Generates a memory initialization file required for bitstream)
* clean (cleans ELF and intermediate files. Should be invoked every time OPTIONS are changed between compilations, expect with generate_hex where it is done automatically)
6. Optionally test updated SW by downloading ELF to Nios2 CPU via JTAG (RTL-SW interface in active FW must be compatible new SW BSP configuration)
3. Optionally test updated SW by directly downloading ELF to CPU via JTAG
~~~~
nios2-download -g --accept-bad-sysid sys_controller.elf
make rv-reprogram
~~~~
Building RTL / bitstream
Building RTL (bitstream)
--------------------------
1. Load the project (ossc.qpf) in Quartus
2. Generate the FPGA bitstream (Processing -> Start Compilation). NOTE: make sure software image (software/sys_controller/mem_init/sys_onchip_memory2_0.hex) is up to date before generating bitstream.
3. Ensure that there are no severe timing violations by looking into Timing Analyzer report
1. Initialize pulpino submodules (once after cloning ossc project)
~~~~
git submodule update --init --recursive ip/pulpino_qsys
~~~~
2. Load the project (ossc.qpf) in Quartus
3. Generate the FPGA bitstream (Processing -> Start Compilation). NOTE: make sure software hex image (software/sys_controller/mem_init/sys_onchip_memory2_0.hex) is up to date before generating bitstream.
4. Ensure that there are no severe timing violations by looking into Timing Analyzer report
If only software image is updated, bitstream can be quickly rebuilt by running "Processing->Update Memory Initialization File" and "Processing->Start->Start Assembler" in Quartus.
@ -105,8 +112,8 @@ make clean && make APP_CFLAGS_DEBUG_LEVEL="-DDEBUG"
~~~~
NOTE: Fw update functionality via SD card is disabled in debug builds due to code space limitations. If audio support is enabled on debug build, other functionality needs to be disabled as well.
2. Program Nios2 CPU via JTAG and open terminal for UART
2. Program CPU via JTAG and open terminal for UART
~~~~
nios2-download -g --accept-bad-sysid sys_controller.elf && nios2-terminal
make rv-reprogram && nios2-terminal
~~~~
Remember to close nios2-terminal after debug session, otherwise any JTAG transactions will hang/fail.

3
ossc.qsf
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@ -57,7 +57,7 @@ set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_location_assignment PIN_25 -to clk27
set_location_assignment PIN_99 -to reset_n
set_location_assignment PIN_99 -to hw_reset_n
set_location_assignment PIN_23 -to ir_rx
#============================================================
@ -245,4 +245,5 @@ set_global_assignment -name QIP_FILE rtl/mux5.qip
set_global_assignment -name CDF_FILE output_files/Chain1.cdf
set_global_assignment -name SIGNALTAP_FILE output_files/ossc_la.stp
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

8
ossc_sw_bsp.project
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@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<CodeLite_Project Name="ossc_sw_bsp" InternalType="">
<CodeLite_Project Name="ossc_sw_bsp" InternalType="" Version="10.0.0">
<Plugins>
<Plugin Name="qmake">
<![CDATA[00020001N0005Debug0000000000000001N0007Release000000000000]]>
@ -280,10 +280,9 @@
<PreBuild/>
<PostBuild/>
<CustomBuild Enabled="yes">
<Target Name="nios2-bsp-editor">nios2-bsp-editor</Target>
<RebuildCommand/>
<CleanCommand>make clean</CleanCommand>
<BuildCommand>nios2-bsp-generate-files --bsp-dir . --settings settings.bsp</BuildCommand>
<BuildCommand>make</BuildCommand>
<PreprocessFileCommand/>
<SingleFileCommand/>
<MakefileGenerationCommand/>
@ -320,10 +319,9 @@
<PreBuild/>
<PostBuild/>
<CustomBuild Enabled="yes">
<Target Name="nios2-bsp-editor">nios2-bsp-editor</Target>
<RebuildCommand/>
<CleanCommand>make clean</CleanCommand>
<BuildCommand>nios2-bsp-generate-files --bsp-dir ./ --settings settings.bsp</BuildCommand>
<BuildCommand>make</BuildCommand>
<PreprocessFileCommand/>
<SingleFileCommand/>
<MakefileGenerationCommand/>

41
rtl/ossc.v
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@ -19,7 +19,7 @@
//`define DEBUG
`define VIDEOGEN
`define CPU_RESET_WIDTH 27 //1us
`define PO_RESET_WIDTH 27 //1us
module ossc (
input clk27,
@ -43,7 +43,7 @@ module ossc (
output HDMI_TX_PCLK,
input HDMI_TX_INT_N,
input HDMI_TX_MODE,
output reset_n,
output hw_reset_n,
output LED_G,
output LED_R,
output LCD_RS,
@ -81,9 +81,10 @@ wire PCLK_out_videogen;
wire DE_out_videogen;
reg [7:0] cpu_reset_ctr = 0;
reg cpu_reset_n = 1'b0;
wire ext_reset_req;
reg [7:0] po_reset_ctr = 0;
reg po_reset_n = 1'b0;
wire jtagm_reset_req;
wire sys_reset_n = (po_reset_n & ~jtagm_reset_req);
reg [7:0] R_in_L, G_in_L, B_in_L;
reg HSYNC_in_L, VSYNC_in_L, FID_in_L;
@ -106,9 +107,9 @@ wire lcd_bl_timeout;
// Latch inputs from TVP7002 (synchronized to PCLK_in)
always @(posedge PCLK_in or negedge reset_n)
always @(posedge PCLK_in or negedge hw_reset_n)
begin
if (!reset_n) begin
if (!hw_reset_n) begin
R_in_L <= 8'h00;
G_in_L <= 8'h00;
B_in_L <= 8'h00;
@ -126,9 +127,9 @@ begin
end
// Insert synchronizers to async inputs (synchronize to CPU clock)
always @(posedge clk27 or negedge cpu_reset_n)
always @(posedge clk27 or negedge po_reset_n)
begin
if (!cpu_reset_n) begin
if (!po_reset_n) begin
btn_L <= 2'b00;
btn_LL <= 2'b00;
ir_rx_L <= 1'b0;
@ -149,16 +150,16 @@ begin
end
end
// CPU reset pulse generation (is this really necessary?)
// Power-on reset pulse generation (not strictly necessary)
always @(posedge clk27)
begin
if (cpu_reset_ctr == `CPU_RESET_WIDTH)
cpu_reset_n <= 1'b1;
if (po_reset_ctr == `PO_RESET_WIDTH)
po_reset_n <= 1'b1;
else
cpu_reset_ctr <= cpu_reset_ctr + 1'b1;
po_reset_ctr <= po_reset_ctr + 1'b1;
end
assign reset_n = sys_ctrl[0]; //HDMI_TX_RST_N in v1.2 PCB
assign hw_reset_n = sys_ctrl[0]; //HDMI_TX_RST_N in v1.2 PCB
`ifdef DEBUG
@ -172,7 +173,7 @@ assign LED_G = (ir_code == 0);
assign SD_DAT[3] = sys_ctrl[7]; //SD_SPI_SS_N
assign LCD_CS_N = sys_ctrl[6];
assign LCD_RS = sys_ctrl[5];
wire lcd_bl_on = sys_ctrl[4]; //reset_n in v1.2 PCB
wire lcd_bl_on = sys_ctrl[4]; //hw_reset_n in v1.2 PCB
wire [1:0] lcd_bl_time = sys_ctrl[3:2];
assign LCD_BL = lcd_bl_on ? (~lcd_bl_timeout | lt_active) : 1'b0;
@ -227,12 +228,12 @@ end
sys sys_inst(
.clk_clk (clk27),
.reset_reset_n (cpu_reset_n & ~ext_reset_req),
.reset_reset_n (sys_reset_n),
.pulpino_0_config_testmode_i (1'b0),
.pulpino_0_config_fetch_enable_i (1'b1),
.pulpino_0_config_clock_gating_i (1'b0),
.pulpino_0_config_boot_addr_i (32'h00010000),
.master_0_master_reset_reset (ext_reset_req),
.master_0_master_reset_reset (jtagm_reset_req),
.i2c_opencores_0_export_scl_pad_io (scl),
.i2c_opencores_0_export_sda_pad_io (sda),
.i2c_opencores_0_export_spi_miso_pad_i (1'b0),
@ -251,7 +252,7 @@ sys sys_inst(
);
scanconverter scanconverter_inst (
.reset_n (reset_n),
.reset_n (hw_reset_n),
.PCLK_in (PCLK_in),
.clk27 (clk27),
.HSYNC_in (HSYNC_in_L),
@ -285,7 +286,7 @@ scanconverter scanconverter_inst (
ir_rcv ir0 (
.clk27 (clk27),
.reset_n (cpu_reset_n),
.reset_n (po_reset_n),
.ir_rx (ir_rx_LL),
.ir_code (ir_code),
.ir_code_ack (),
@ -310,7 +311,7 @@ lat_tester lt0 (
`ifdef VIDEOGEN
videogen vg0 (
.clk27 (clk27),
.reset_n (cpu_reset_n & videogen_sel),
.reset_n (po_reset_n & videogen_sel),
.lt_active (lt_active),
.lt_mode (lt_mode_synced),
.R_out (R_out_videogen),

4
software/ossc_sw.project
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@ -121,7 +121,7 @@
</Compiler>
<Linker Options="" Required="yes"/>
<ResourceCompiler Options="" Required="no"/>
<General OutputFile="" IntermediateDirectory="./Debug" Command="nios2-download -g --accept-bad-sysid sys_controller.elf &amp;&amp; nios2-terminal" CommandArguments="" UseSeparateDebugArgs="no" DebugArguments="" WorkingDirectory="$(ProjectPath)/sys_controller" PauseExecWhenProcTerminates="yes" IsGUIProgram="no" IsEnabled="yes"/>
<General OutputFile="" IntermediateDirectory="./Debug" Command="make rv-reprogram &amp;&amp; nios2-terminal" CommandArguments="" UseSeparateDebugArgs="no" DebugArguments="" WorkingDirectory="$(ProjectPath)/sys_controller" PauseExecWhenProcTerminates="yes" IsGUIProgram="no" IsEnabled="yes"/>
<BuildSystem Name="Default"/>
<Environment EnvVarSetName="&lt;Use Defaults&gt;" DbgSetName="&lt;Use Defaults&gt;">
<![CDATA[]]>
@ -135,6 +135,7 @@
<PostBuild/>
<CustomBuild Enabled="yes">
<Target Name="diy-audio-debug">make ENABLE_AUDIO=y APP_CFLAGS_DEBUG_LEVEL="-DDEBUG"</Target>
<Target Name="Ack BSP update">cd ../sys_controller_bsp &amp;&amp; touch public.mk Makefile</Target>
<RebuildCommand/>
<CleanCommand>make clean</CleanCommand>
<BuildCommand>make APP_CFLAGS_DEBUG_LEVEL="-DDEBUG"</BuildCommand>
@ -180,6 +181,7 @@
<Target Name="compile_image">make generate_hex</Target>
<Target Name="Build_jp">make OSDLANG=JP</Target>
<Target Name="Build_audio">make ENABLE_AUDIO=y</Target>
<Target Name="Ack BSP update">cd ../sys_controller_bsp &amp;&amp; touch public.mk Makefile</Target>
<RebuildCommand/>
<CleanCommand>make clean</CleanCommand>
<BuildCommand>make</BuildCommand>

1
software/sys_controller/Makefile
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@ -165,6 +165,7 @@ else
C_SRCS += ossc/menu.c
endif
C_SRCS += ossc/userdata.c
C_SRCS += ossc/utils.c
C_SRCS += ulibSD/sd_io.c
C_SRCS += ulibSD/spi_io.c
CXX_SRCS :=

12788
software/sys_controller/mem_init/sys_onchip_memory2_0.hex
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File diff suppressed because it is too large Load Diff

4
software/sys_controller_bsp/HAL/src/alt_main.c
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@ -39,7 +39,7 @@
#include "sys/alt_dev.h"
#include "sys/alt_sys_init.h"
#include "sys/alt_irq.h"
//#include "sys/alt_irq.h"
#include "sys/alt_dev.h"
#include "os/alt_hooks.h"
@ -51,6 +51,8 @@
#include "sys/alt_log_printf.h"
extern void alt_irq_init ( const void* base );
extern void _do_ctors(void);
extern void _do_dtors(void);

19
software/sys_controller_bsp/Makefile
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@ -439,7 +439,6 @@ ifneq ($(wildcard $(NEWLIB_DIR)),)
endif
@$(ECHO) [BSP clean complete]
#------------------------------------------------------------------------------
# BUILD PRE/POST PROCESS
#------------------------------------------------------------------------------
@ -470,14 +469,7 @@ Makefile: $(wildcard $(SETTINGS_FILE))
@$(ECHO) Makefile not up to date.
@$(ECHO) $(SETTINGS_FILE) has been modified since the BSP Makefile was generated.
@$(ECHO)
@$(ECHO) Generate the BSP to update the Makefile, and then build again.
@$(ECHO)
@$(ECHO) To generate from Eclipse:
@$(ECHO) " 1. Right-click the BSP project."
@$(ECHO) " 2. In the Nios II Menu, click Generate BSP."
@$(ECHO)
@$(ECHO) To generate from the command line:
@$(ECHO) " nios2-bsp-generate-files --settings=<settings file> --bsp-dir=<target bsp files directory>"
@$(ECHO) Update system.h etc. BSP files manually, then run \"touch public.mk Makefile\" on BSP dir.
@$(ECHO)
@exit 1
@ -489,14 +481,7 @@ public.mk: $(wildcard $(SOPC_FILE))
@$(ECHO) Makefile not up to date.
@$(ECHO) $(SOPC_FILE) has been modified since the BSP was generated.
@$(ECHO)
@$(ECHO) Generate the BSP to update the Makefile, and then build again.
@$(ECHO)
@$(ECHO) To generate from Eclipse:
@$(ECHO) " 1. Right-click the BSP project."
@$(ECHO) " 2. In the Nios II Menu, click Generate BSP."
@$(ECHO)
@$(ECHO) To generate from the command line:
@$(ECHO) " nios2-bsp-generate-files --settings=<settings file> --bsp-dir=<target bsp files directory>"
@$(ECHO) Update system.h etc. BSP files manually, then run \"touch public.mk Makefile\" on BSP dir.
@$(ECHO)
@exit 1

BIN
software/sys_controller_bsp/libhal_bsp.a
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4
sys.sopcinfo
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@ -1,11 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="sys" kind="sys" version="1.0" fabric="QSYS">
<!-- Format version 17.1 590 (Future versions may contain additional information.) -->
<!-- 2018.10.07.02:44:40 -->
<!-- 2018.10.08.00:13:33 -->
<!-- A collection of modules and connections -->
<parameter name="AUTO_GENERATION_ID">
<type>java.lang.Integer</type>
<value>1538869480</value>
<value>1538946813</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>