3 Commits

Author	SHA1	Message	Date
marqs	85c295c5e2	make pll_reconfig more robust	2019-10-12 22:56:10 +03:00
marqs	b22365af20	add timeout to pll_reconfig and update postprocess pipeline diagram	2019-10-07 23:20:44 +03:00
marqs	9d496383c3	optimize clock network ... * replace all clock muxes with a single cycloneive_clkctrl to minimize skew * use a single dynamically configured PLL to comply with cycloneive_clkctrl	2019-10-06 23:54:32 +03:00