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209130b167
- integrate mask and border generation more deeply into the post processing chain - delay RLPF by one PP stage (reduce logic length after large mux) - synthesise a registers after several adder logics |
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| .. | ||
| ir_rcv.v | ||
| lat_tester_includes.v | ||
| lat_tester.v | ||
| linebuf.qip | ||
| linebuf.v | ||
| lpm_mult_4_hybr_ref_bb.v | ||
| lpm_mult_4_hybr_ref_pre_bb.v | ||
| lpm_mult_4_hybr_ref_pre.qip | ||
| lpm_mult_4_hybr_ref_pre.v | ||
| lpm_mult_4_hybr_ref.qip | ||
| lpm_mult_4_hybr_ref.v | ||
| lpm_mult_4_sl_bb.v | ||
| lpm_mult_4_sl.qip | ||
| lpm_mult_4_sl.v | ||
| ossc.v | ||
| pll_2x.ppf | ||
| pll_2x.qip | ||
| pll_2x.v | ||
| pll_3x.ppf | ||
| pll_3x.qip | ||
| pll_3x.v | ||
| scanconverter.v | ||
| timescale.v | ||
| videogen.v | ||