marqs 9d496383c3 optimize clock network ... * replace all clock muxes with a single cycloneive_clkctrl to minimize skew * use a single dynamically configured PLL to comply with cycloneive_clkctrl		2019-10-06 23:54:32 +03:00
..
it6613	fix audio infoframe content to comply with HDMI spec	2019-08-24 10:54:13 +03:00
mem_init	optimize clock network	2019-10-06 23:54:32 +03:00
memory	move bitswap inside epcq_controller driver	2018-10-09 23:16:37 +03:00
ossc	optimize clock network	2019-10-06 23:54:32 +03:00
pcm1862	pcm1862: add pre-ADC gain setting	2018-03-02 23:11:52 +02:00
spi_charlcd	Update latency tester	2017-10-28 12:10:54 +03:00
ths7353	enable 35MHz video LPF for 720p & 1080i in auto mode	2019-03-16 01:20:16 +02:00
tvp7002	add 384x240 optimized mode	2019-08-30 00:29:30 +03:00
ulibSD	Update latency tester	2017-10-28 12:10:54 +03:00
crt0.boot_E.S	switch to RV32E	2018-10-30 01:31:40 +02:00
crt0.boot.S	integrate zero-riscy	2018-10-06 13:19:12 +03:00
link.common.ld	integrate zero-riscy	2018-10-06 13:19:12 +03:00
link.riscv.ld	integrate zero-riscy	2018-10-06 13:19:12 +03:00
Makefile	first OSD implementation	2019-10-03 02:03:43 +03:00
pulpino.h	integrate zero-riscy	2018-10-06 13:19:12 +03:00