emulate RAM refresh lost CPU cycles

rtl/apple1_mist.sv

@@ -2,10 +2,9 @@
 //
 // Forked from Gehstock's implementation https://github.com/Gehstock/Mist_FPGA
 //
-//
 
+// TODO display: crosstalk artifact (selectable)
 // TODO use a CPU that allows illegal instructions
-// TODO ram refresh lost CPU cycles
 // TODO power on-off key ? init ram with values
 // TODO ram powerup initial values
 // TODO reorganize file structure
@@ -168,11 +167,11 @@ downloader
    .ROM_done    ( ROM_loaded      ),	
 	         
    // external ram interface
-   .clk     ( sys_clock     ),
+   .clk     ( sys_clock      ),
-	.clk_ena ( cpu_clken     ),
+	.clk_ena ( cpu_clken_noRF ),
-   .wr      ( download_wr   ),
+   .wr      ( download_wr    ),
-   .addr    ( download_addr ),
+   .addr    ( download_addr  ),
-   .data    ( download_data )	
+   .data    ( download_data  )	
 );
 
 /******************************************************************************************/
@@ -561,20 +560,21 @@ sdram sdram (
 /******************************************************************************************/
 /******************************************************************************************/
 
-wire cpu_clken;    // provides the cpu clock enable signal derived from main clock
+wire pixel_clken;    // provides the cpu clock enable signal derived from main clock
-wire pixel_clken;  // provides the cpu clock enable signal derived from main clock
+wire cpu_clken;      // provides the cpu clock enable signal derived from main clock, ram refresh accounted
-wire cpu_clock;
+wire cpu_clken_noRF; // provides the cpu clock enable signal derived from main clock, without accounting for refresh cycles
+wire cpu_clock;      // cpu clock for the sdram controller sync
 
 clock clock(
   .sys_clock  ( sys_clock     ),   // input: main clock
   .reset      ( reset_button  ),   // input: reset signal
 
-  .cpu_clock  ( cpu_clock     ),  
+  .cpu_clock      ( cpu_clock      ),  
-  .cpu_clken  ( cpu_clken     ),   // output: cpu clock enable (phi2)
+  .cpu_clken      ( cpu_clken      ),   // output: cpu clock enable (phi2)
-  .pixel_clken( pixel_clken   )    // output: pixel clock enable
+  .cpu_clken_noRF ( cpu_clken_noRF ),   // output: cpu clock enable (phi0)
+  .pixel_clken    ( pixel_clken    )    // output: pixel clock enable
 );
 
-
 /******************************************************************************************/
 /******************************************************************************************/
 /***************************************** @vdp *******************************************/

rtl/clock.v

@@ -3,16 +3,17 @@ module clock
 (
    input sys_clock,        // master clock at cpu x 7 x 8
    input reset,            // reset
-   
+      
-   output cpu_clken,     // 1MHz clock enable for the CPU 
+	output pixel_clken,     // 7MHz clock enable for the display
-	output pixel_clken,   // 7MHz clock enable for the display
+	output cpu_clken,       // 1MHz clock enable for the CPU, ram refresh cycles inlcuded
+	output cpu_clken_noRF,  // 1MHz clock (pure, without refresh cycles)
 		
 	output cpu_clock
 );
 
 localparam CPU_DIVISOR     = 56;  // (sys_clock / CPU_DIVISOR)   = 1 MHz
 localparam PIXEL_DIVISOR   =  8;  // (sys_clock / PIXEL_DIVISOR) = 7 MHz
-localparam REFRESH_DIVISOR = 65;  // 
+localparam REFRESH_DIVISOR = 65;  // counts 65 clock ticks (one complete scanline at phi0 speed)
 
 	reg [5:0] counter_cpu;
 	reg [2:0] counter_pixel;
@@ -39,8 +40,12 @@ localparam REFRESH_DIVISOR = 65;  //
 		end
 	end
 	
-	assign cpu_clken   = counter_cpu   == 0 /*&& counter_refresh > 3*/;
+	// the ram refresh cycle is activated by the horizontal counter on every 10 character
-	assign pixel_clken = counter_pixel == 0;
+	wire RF = counter_refresh == 25 || counter_refresh == 35 || counter_refresh == 45 || counter_refresh == 55;
+	
+	assign cpu_clken      = counter_cpu   == 0 && !RF;
+	assign cpu_clken_noRF = counter_cpu   == 0;
+	assign pixel_clken    = counter_pixel == 0;
 	
 	assign cpu_clock = counter_pixel < 4 ? 1 : 0;