15 Commits

Author	SHA1	Message	Date
Olof Kindgren	2226afe669	Expose ROM/RAM files as top-level parameters ... This allows file names to be overridden at compile-time. It also gets rid of the ifdef SIM in the verilog components	2018-02-12 14:04:00 +01:00
Alan Garfield	a4f13a87fe	updated ROM paths to handle new board/buildenv structure	2018-02-12 08:26:57 +11:00
Niels Moseley	237d35491a	Fixed Quartus VGA reversal bug/feature. Removed bit reversing logic and created bit-reversed font rom hex file	2018-02-08 17:51:30 +01:00
Niels Moseley	f76134bcf1	Added VGA font rom in hex to (hopefully) solve the endianess problems between Yosys/Quartus	2018-02-07 19:22:00 +01:00
Niels Moseley	dd2c480675	Fixed reg/wire problems for Quartus.	2018-02-07 17:12:27 +01:00
Alan Garfield	9371303789	Fixed minor verilator complaint	2018-02-08 01:06:35 +11:00
Alan Garfield	fdc93fb0d2	Hardware scrolling seems to be working!	2018-02-08 00:40:43 +11:00
Alan Garfield	6f7812f51d	Added defines to choose display mode of fonts	2018-02-06 00:35:30 +11:00
Alan Garfield	25aff9cdc3	VGA module works. Still no hardware scrolling though	2018-02-06 00:29:56 +11:00
Alan Garfield	7b3c65b8d9	Fixed issue with yosys compile	2018-02-05 00:24:12 +11:00
Alan Garfield	20919fa726	wip of the pipeline VGA module. stupid yosys bug, but testbench looks ok	2018-02-05 00:12:06 +11:00
Alan Garfield	2432225d01	Initial VGA working with the apple one output. YAY!	2018-01-31 00:48:47 +11:00
Alan Garfield	451bff1592	fiddled the vga module a little	2018-01-30 00:19:21 +11:00
Alan Garfield	4fef9bc10b	Initial VGA module, still WIP, just outputs fixed VRAM	2018-01-29 22:53:16 +11:00
Alan Garfield	7bdccf3d1a	move things around.	2018-01-27 00:21:05 +11:00